:orphan: .. title:: RISCV_PMP .. option:: CONFIG_RISCV_PMP *RISC-V PMP Support* Type: ``bool`` Help ==== MCU implements Physical Memory Protection. Memory protection against read-only area writing is natively supported on real HW. Direct dependencies =================== \ :option:`RISCV ` *(Includes any dependencies from ifs and menus.)* Default ======= - n Symbols selected by this symbol =============================== - \ :option:`THREAD_STACK_INFO ` - \ :option:`CPU_HAS_MPU ` - \ :option:`MPU ` - \ :option:`SRAM_REGION_PERMISSIONS ` - \ :option:`ARCH_MEM_DOMAIN_SYNCHRONOUS_API ` if \ :option:`USERSPACE ` - \ :option:`PMP_POWER_OF_TWO_ALIGNMENT ` if \ :option:`USERSPACE ` Symbols that select this symbol =============================== - \ :option:`CORE_E31 ` Kconfig definition ================== .. highlight:: kconfig At ``arch/riscv/Kconfig:115`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:29`` → ``arch/Kconfig:12`` Menu path: (Top) → RISCV Options → RISCV Processor Options .. parsed-literal:: menuconfig RISCV_PMP bool "RISC-V PMP Support" default n select \ :option:`THREAD_STACK_INFO ` select \ :option:`CPU_HAS_MPU ` select \ :option:`MPU ` select \ :option:`SRAM_REGION_PERMISSIONS ` select \ :option:`ARCH_MEM_DOMAIN_SYNCHRONOUS_API ` if \ :option:`USERSPACE ` select \ :option:`PMP_POWER_OF_TWO_ALIGNMENT ` if \ :option:`USERSPACE ` depends on \ :option:`RISCV ` help MCU implements Physical Memory Protection. Memory protection against read-only area writing is natively supported on real HW. *(The 'depends on' condition includes propagated dependencies from ifs and menus.)*