:orphan:

.. title:: SOC_OPENISA_RV32M1_RISCV32

.. option:: CONFIG_SOC_OPENISA_RV32M1_RISCV32

*OpenISA RV32M1 RISC-V cores*

Type: ``bool``

Help
====

Enable support for OpenISA RV32M1 RISC-V processors. Choose
this option to target the RI5CY or ZERO-RISCY core. This
option should not be used to target either Arm core.

Direct dependencies
===================

\ :ref:`<choice: SoC/CPU/Configuration Selection> <choice_43>`

*(Includes any dependencies from ifs and menus.)*

Symbols selected by this symbol
===============================

- \ :option:`RISCV <CONFIG_RISCV>`
- \ :option:`XIP <CONFIG_XIP>`
- \ :option:`HAS_RV32M1_LPUART <CONFIG_HAS_RV32M1_LPUART>`
- \ :option:`HAS_RV32M1_LPI2C <CONFIG_HAS_RV32M1_LPI2C>`
- \ :option:`HAS_RV32M1_LPSPI <CONFIG_HAS_RV32M1_LPSPI>`
- \ :option:`HAS_RV32M1_TPM <CONFIG_HAS_RV32M1_TPM>`
- \ :option:`ATOMIC_OPERATIONS_C <CONFIG_ATOMIC_OPERATIONS_C>`
- \ :option:`VEGA_SDK_HAL <CONFIG_VEGA_SDK_HAL>`
- \ :option:`RISCV_SOC_INTERRUPT_INIT <CONFIG_RISCV_SOC_INTERRUPT_INIT>`
- \ :option:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`
- \ :option:`HAS_RV32M1_FTFX <CONFIG_HAS_RV32M1_FTFX>`
- \ :option:`HAS_FLASH_LOAD_OFFSET <CONFIG_HAS_FLASH_LOAD_OFFSET>`

Kconfig definition
==================

.. highlight:: kconfig

At ``soc/riscv/openisa_rv32m1/Kconfig.soc:4``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:28`` → ``soc/Kconfig:6`` → ``/home/runner/work/bridle/bridle/workspace/build/Kconfig/Kconfig.soc:1``

Menu path: (Top) → SoC/CPU/Configuration Selection

.. parsed-literal::

    config SOC_OPENISA_RV32M1_RISCV32
    	bool "OpenISA RV32M1 RISC-V cores"
    	select \ :option:`RISCV <CONFIG_RISCV>`
    	select \ :option:`XIP <CONFIG_XIP>`
    	select \ :option:`HAS_RV32M1_LPUART <CONFIG_HAS_RV32M1_LPUART>`
    	select \ :option:`HAS_RV32M1_LPI2C <CONFIG_HAS_RV32M1_LPI2C>`
    	select \ :option:`HAS_RV32M1_LPSPI <CONFIG_HAS_RV32M1_LPSPI>`
    	select \ :option:`HAS_RV32M1_TPM <CONFIG_HAS_RV32M1_TPM>`
    	select \ :option:`ATOMIC_OPERATIONS_C <CONFIG_ATOMIC_OPERATIONS_C>`
    	select \ :option:`VEGA_SDK_HAL <CONFIG_VEGA_SDK_HAL>`
    	select \ :option:`RISCV_SOC_INTERRUPT_INIT <CONFIG_RISCV_SOC_INTERRUPT_INIT>`
    	select \ :option:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`
    	select \ :option:`HAS_RV32M1_FTFX <CONFIG_HAS_RV32M1_FTFX>`
    	select \ :option:`HAS_FLASH_LOAD_OFFSET <CONFIG_HAS_FLASH_LOAD_OFFSET>`
    	depends on \ :ref:`<choice: SoC/CPU/Configuration Selection> <choice_43>`
    	help
    	  Enable support for OpenISA RV32M1 RISC-V processors. Choose
    	  this option to target the RI5CY or ZERO-RISCY core. This
    	  option should not be used to target either Arm core.

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*