:orphan:

.. title:: 2ND_LVL_ISR_TBL_OFFSET

.. option:: CONFIG_2ND_LVL_ISR_TBL_OFFSET

*Offset in _sw_isr_table for level 2 interrupts*

Type: ``int``

Help
====

This is the offset in _sw_isr_table, the generated ISR handler table,
where storage for 2nd level interrupt ISRs begins. This is
typically allocated after ISRs for level 1 interrupts.

Direct dependencies
===================

\ :option:`BOARD_INTEL_ADSP_CAVS15 <CONFIG_BOARD_INTEL_ADSP_CAVS15>` || \ :option:`BOARD_INTEL_ADSP_CAVS18 <CONFIG_BOARD_INTEL_ADSP_CAVS18>` || \ :option:`BOARD_INTEL_ADSP_CAVS20 <CONFIG_BOARD_INTEL_ADSP_CAVS20>` || \ :option:`BOARD_INTEL_ADSP_CAVS25 <CONFIG_BOARD_INTEL_ADSP_CAVS25>` || \ :option:`BOARD_INTEL_S1000_CRB <CONFIG_BOARD_INTEL_S1000_CRB>` || (\ :option:`MULTI_LEVEL_INTERRUPTS <CONFIG_MULTI_LEVEL_INTERRUPTS>` && \ :option:`SOC_OPENISA_RV32M1_RISCV32 <CONFIG_SOC_OPENISA_RV32M1_RISCV32>`) || \ :option:`SOC_SERIES_RISCV32_MIV <CONFIG_SOC_SERIES_RISCV32_MIV>` || \ :option:`SOC_SERIES_RISCV_SIFIVE_FREEDOM <CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM>` || \ :option:`SOC_SERIES_RISCV_VIRT <CONFIG_SOC_SERIES_RISCV_VIRT>` || \ :option:`2ND_LEVEL_INTERRUPTS <CONFIG_2ND_LEVEL_INTERRUPTS>`

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- 21
- 21
- 21
- 21
- 21
- 32
- 12
- 12
- 12
- 0

Kconfig definitions
===================

.. highlight:: kconfig

At ``boards/xtensa/intel_adsp_cavs15/Kconfig.defconfig:32``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 21
    	depends on \ :option:`BOARD_INTEL_ADSP_CAVS15 <CONFIG_BOARD_INTEL_ADSP_CAVS15>`

----

At ``boards/xtensa/intel_adsp_cavs18/Kconfig.defconfig:32``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 21
    	depends on \ :option:`BOARD_INTEL_ADSP_CAVS18 <CONFIG_BOARD_INTEL_ADSP_CAVS18>`

----

At ``boards/xtensa/intel_adsp_cavs20/Kconfig.defconfig:32``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 21
    	depends on \ :option:`BOARD_INTEL_ADSP_CAVS20 <CONFIG_BOARD_INTEL_ADSP_CAVS20>`

----

At ``boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig:32``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 21
    	depends on \ :option:`BOARD_INTEL_ADSP_CAVS25 <CONFIG_BOARD_INTEL_ADSP_CAVS25>`

----

At ``boards/xtensa/intel_s1000_crb/Kconfig.defconfig:38``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 21
    	depends on \ :option:`BOARD_INTEL_S1000_CRB <CONFIG_BOARD_INTEL_S1000_CRB>`

----

At ``soc/riscv/openisa_rv32m1/Kconfig.defconfig:52``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:19`` → ``/home/runner/work/bridle/bridle/workspace/build/Kconfig/Kconfig.soc.defconfig:1``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 32
    	depends on \ :option:`MULTI_LEVEL_INTERRUPTS <CONFIG_MULTI_LEVEL_INTERRUPTS>` && \ :option:`SOC_OPENISA_RV32M1_RISCV32 <CONFIG_SOC_OPENISA_RV32M1_RISCV32>`

----

At ``soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series:20``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:19`` → ``/home/runner/work/bridle/bridle/workspace/build/Kconfig/Kconfig.soc.defconfig:1`` → ``soc/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 12
    	depends on \ :option:`SOC_SERIES_RISCV32_MIV <CONFIG_SOC_SERIES_RISCV32_MIV>`

----

At ``soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:20``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:19`` → ``/home/runner/work/bridle/bridle/workspace/build/Kconfig/Kconfig.soc.defconfig:1`` → ``soc/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 12
    	depends on \ :option:`SOC_SERIES_RISCV_SIFIVE_FREEDOM <CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM>`

----

At ``soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series:21``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:19`` → ``/home/runner/work/bridle/bridle/workspace/build/Kconfig/Kconfig.soc.defconfig:1`` → ``soc/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int
    	default 12
    	depends on \ :option:`SOC_SERIES_RISCV_VIRT <CONFIG_SOC_SERIES_RISCV_VIRT>`

----

At ``drivers/interrupt_controller/Kconfig.multilevel:36``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:26`` → ``drivers/interrupt_controller/Kconfig:49``

Menu path: (Top) → Device Drivers → Interrupt Controllers → Multi-level interrupt support → Second-level interrupt support

.. parsed-literal::

    config 2ND_LVL_ISR_TBL_OFFSET
    	int "Offset in _sw_isr_table for level 2 interrupts"
    	default 0
    	depends on \ :option:`2ND_LEVEL_INTERRUPTS <CONFIG_2ND_LEVEL_INTERRUPTS>`
    	help
    	  This is the offset in _sw_isr_table, the generated ISR handler table,
    	  where storage for 2nd level interrupt ISRs begins. This is
    	  typically allocated after ISRs for level 1 interrupts.

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*