:orphan:

.. title:: ARM_CUSTOM_INTERRUPT_CONTROLLER

.. option:: CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER

*(No prompt -- not directly user assignable.)*

Type: ``bool``

Help
====

This option indicates that the ARM CPU is connected to a custom (i.e.
non-GIC) interrupt controller.

A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
allow interfacing to a custom external interrupt controller and this
option must be selected when such cores are connected to an interrupt
controller that is not the ARM Generic Interrupt Controller (GIC).

When this option is selected, the architecture interrupt control
functions are mapped to the SoC interrupt control interface, which is
implemented at the SoC level.

N.B. This option is only applicable to the Cortex-A and Cortex-R
     family cores. The Cortex-M family cores are always equipped with
     the ARM Nested Vectored Interrupt Controller (NVIC).

Direct dependencies
===================

!\ :option:`CPU_CORTEX_M <CONFIG_CPU_CORTEX_M>` && \ :option:`ARM <CONFIG_ARM>`

*(Includes any dependencies from ifs and menus.)*

Defaults
========

No defaults. Implicitly defaults to ``n``.

Kconfig definition
==================

.. highlight:: kconfig

At ``arch/arm/Kconfig:21``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:29`` → ``arch/Kconfig:12``

Menu path: (Top) → ARM Options

.. parsed-literal::

    config ARM_CUSTOM_INTERRUPT_CONTROLLER
    	bool
    	depends on !\ :option:`CPU_CORTEX_M <CONFIG_CPU_CORTEX_M>` && \ :option:`ARM <CONFIG_ARM>`
    	help
    	  This option indicates that the ARM CPU is connected to a custom (i.e.
    	  non-GIC) interrupt controller.
	  
    	  A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
    	  allow interfacing to a custom external interrupt controller and this
    	  option must be selected when such cores are connected to an interrupt
    	  controller that is not the ARM Generic Interrupt Controller (GIC).
	  
    	  When this option is selected, the architecture interrupt control
    	  functions are mapped to the SoC interrupt control interface, which is
    	  implemented at the SoC level.
	  
    	  N.B. This option is only applicable to the Cortex-A and Cortex-R
    	       family cores. The Cortex-M family cores are always equipped with
    	       the ARM Nested Vectored Interrupt Controller (NVIC).

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*