:orphan: .. title:: CLOCK_STM32_PLL_M_DIVISOR .. option:: CONFIG_CLOCK_STM32_PLL_M_DIVISOR *Division factor for PLL VCO input clock* *PLL divisor* *PLL divisor* *PLL divisor* *PLL divisor* Type: ``int`` Help ==== PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 Help ==== PLL divisor, allowed values: 0-63. Help ==== PLL divisor, L4: allowed values: 1-8. PLL VCO input ranges from 4 to 16MHz L5: allowed values: 1-16. PLL VCO input ranges from 4 to 16MHz WB: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz Help ==== PLL divisor, allowed values: 1-8. Help ==== PLL divisor, allowed values: 1-16. Direct dependencies =================== (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32F2X ` || \ :option:`SOC_SERIES_STM32F4X ` || \ :option:`SOC_SERIES_STM32F7X `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32H7X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32L4X ` || \ :option:`SOC_SERIES_STM32L5X ` || \ :option:`SOC_SERIES_STM32WBX `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G0X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G4X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) *(Includes any dependencies from ifs and menus.)* Defaults ======== - 8 - 32 - 1 - 1 - 4 Kconfig definitions =================== .. highlight:: kconfig At ``drivers/clock_control/Kconfig.stm32f2_f4_f7:8`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:132`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_M_DIVISOR int "Division factor for PLL VCO input clock" range 2 63 default 8 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32F2X ` || \ :option:`SOC_SERIES_STM32F4X ` || \ :option:`SOC_SERIES_STM32F7X `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 ---- At ``drivers/clock_control/Kconfig.stm32h7:67`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:133`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 0 63 default 32 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32H7X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL divisor, allowed values: 0-63. ---- At ``drivers/clock_control/Kconfig.stm32l4_l5_wb:8`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:135`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 8 if \ :option:`SOC_SERIES_STM32L4X ` || \ :option:`SOC_SERIES_STM32WBX ` range 1 16 if \ :option:`SOC_SERIES_STM32L5X ` default 1 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32L4X ` || \ :option:`SOC_SERIES_STM32L5X ` || \ :option:`SOC_SERIES_STM32WBX `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL divisor, L4: allowed values: 1-8. PLL VCO input ranges from 4 to 16MHz L5: allowed values: 1-16. PLL VCO input ranges from 4 to 16MHz WB: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz ---- At ``drivers/clock_control/Kconfig.stm32g0:17`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:136`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 8 default 1 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G0X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL divisor, allowed values: 1-8. ---- At ``drivers/clock_control/Kconfig.stm32g4:8`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:137`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 16 default 4 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G4X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL divisor, allowed values: 1-16. *(The 'depends on' condition includes propagated dependencies from ifs and menus.)*