:orphan: .. title:: CLOCK_STM32_PLL_P_DIVISOR .. option:: CONFIG_CLOCK_STM32_PLL_P_DIVISOR *PLL division factor for main system clock* *PLL P Divisor* *PLL P Divisor* *PLL P Divisor* *PLL P Divisor* Type: ``int`` Help ==== PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8 Help ==== PLL P Output divisor, allowed values: 1-128. Help ==== PLL P Output divisor L4: allowed values: 0, 7, 17. PLLP do not exceed 80MHz L5: allowed values: 0, 7, 17. PLLP do not exceed 80MHz WB: allowed values: 0, 2-32. PLLP do not exceed 64MHz Help ==== PLL P VCO divisor, allowed values: 2-32. Help ==== PLL P Output divisor, allowed values: 7, 17. Direct dependencies =================== (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32F2X ` || \ :option:`SOC_SERIES_STM32F4X ` || \ :option:`SOC_SERIES_STM32F7X `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32H7X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32L4X ` || \ :option:`SOC_SERIES_STM32L5X ` || \ :option:`SOC_SERIES_STM32WBX `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G0X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G4X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) *(Includes any dependencies from ifs and menus.)* Defaults ======== - 4 - 2 - 7 - 2 - 7 Kconfig definitions =================== .. highlight:: kconfig At ``drivers/clock_control/Kconfig.stm32f2_f4_f7:31`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:132`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_P_DIVISOR int "PLL division factor for main system clock" range 2 8 default 4 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32F2X ` || \ :option:`SOC_SERIES_STM32F4X ` || \ :option:`SOC_SERIES_STM32F7X `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8 ---- At ``drivers/clock_control/Kconfig.stm32h7:83`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:133`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 1 128 default 2 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32H7X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL P Output divisor, allowed values: 1-128. ---- At ``drivers/clock_control/Kconfig.stm32l4_l5_wb:32`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:135`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 0 17 if \ :option:`SOC_SERIES_STM32L4X ` || \ :option:`SOC_SERIES_STM32L5X ` range 0 32 if \ :option:`SOC_SERIES_STM32WBX ` default 7 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32L4X ` || \ :option:`SOC_SERIES_STM32L5X ` || \ :option:`SOC_SERIES_STM32WBX `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL P Output divisor L4: allowed values: 0, 7, 17. PLLP do not exceed 80MHz L5: allowed values: 0, 7, 17. PLLP do not exceed 80MHz WB: allowed values: 0, 2-32. PLLP do not exceed 64MHz ---- At ``drivers/clock_control/Kconfig.stm32g0:25`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:136`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 2 32 default 2 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G0X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL P VCO divisor, allowed values: 2-32. ---- At ``drivers/clock_control/Kconfig.stm32g4:24`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:137`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 7 17 default 7 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G4X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL P Output divisor, allowed values: 7, 17. *(The 'depends on' condition includes propagated dependencies from ifs and menus.)*