:orphan: .. title:: CLOCK_STM32_PLL_Q_DIVISOR .. option:: CONFIG_CLOCK_STM32_PLL_Q_DIVISOR *Division factor for OTG FS, SDIO and RNG clocks* *PLL Q Divisor* *PLL Q Divisor* *PLL Q Divisor* *PLL Q Divisor* Type: ``int`` Help ==== The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15 Help ==== PLL Q Output divisor, allowed values: 1-128. Help ==== PLL Q Output divisor L4: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz L5: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz WB: allowed values: 0, 2-8. PLLQ do not exceed 64MHz Help ==== PLL Q VCO divisor, allowed values: 2-8. Limited to STM32G0X1 variants. Help ==== PLL Q Output divisor, allowed values: 2, 4, 6, 8. Direct dependencies =================== (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32F2X ` || \ :option:`SOC_SERIES_STM32F4X ` || \ :option:`SOC_SERIES_STM32F7X `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32H7X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32L4X ` || \ :option:`SOC_SERIES_STM32L5X ` || \ :option:`SOC_SERIES_STM32WBX `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_STM32G031XX ` || \ :option:`SOC_STM32G071XX `) && \ :option:`SOC_SERIES_STM32G0X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) || (\ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G4X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL `) *(Includes any dependencies from ifs and menus.)* Defaults ======== - 7 - 2 - 2 - 2 - 2 Kconfig definitions =================== .. highlight:: kconfig At ``drivers/clock_control/Kconfig.stm32f2_f4_f7:40`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:132`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_Q_DIVISOR int "Division factor for OTG FS, SDIO and RNG clocks" range 2 15 default 7 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32F2X ` || \ :option:`SOC_SERIES_STM32F4X ` || \ :option:`SOC_SERIES_STM32F7X `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15 ---- At ``drivers/clock_control/Kconfig.stm32h7:91`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:133`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" range 1 128 default 2 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32H7X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL Q Output divisor, allowed values: 1-128. ---- At ``drivers/clock_control/Kconfig.stm32l4_l5_wb:44`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:135`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" range 0 8 default 2 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_SERIES_STM32L4X ` || \ :option:`SOC_SERIES_STM32L5X ` || \ :option:`SOC_SERIES_STM32WBX `) && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL Q Output divisor L4: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz L5: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz WB: allowed values: 0, 2-8. PLLQ do not exceed 64MHz ---- At ``drivers/clock_control/Kconfig.stm32g0:33`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:136`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" range 2 8 default 2 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :option:`SOC_STM32G031XX ` || \ :option:`SOC_STM32G071XX `) && \ :option:`SOC_SERIES_STM32G0X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL Q VCO divisor, allowed values: 2-8. Limited to STM32G0X1 variants. ---- At ``drivers/clock_control/Kconfig.stm32g4:32`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``drivers/Kconfig:54`` → ``drivers/clock_control/Kconfig:25`` → ``drivers/clock_control/Kconfig.stm32:137`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. parsed-literal:: config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" range 2 8 default 2 depends on \ :option:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :option:`SOC_SERIES_STM32G4X ` && \ :option:`CLOCK_CONTROL_STM32_CUBE ` && \ :option:`CLOCK_CONTROL ` help PLL Q Output divisor, allowed values: 2, 4, 6, 8. *(The 'depends on' condition includes propagated dependencies from ifs and menus.)*