:orphan:

.. title:: MCG_FRDIV

.. option:: CONFIG_MCG_FRDIV

*FLL external reference divider*

Type: ``int``

Help
====

Selects the amount to divide down the external reference clock for the
FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
kHz.

Direct dependencies
===================

\ :option:`BOARD_FRDM_KL25Z <CONFIG_BOARD_FRDM_KL25Z>` || \ :option:`BOARD_FRDM_KW41Z <CONFIG_BOARD_FRDM_KW41Z>` || \ :option:`BOARD_HEXIWEAR_KW40Z <CONFIG_BOARD_HEXIWEAR_KW40Z>` || (\ :option:`HAS_MCG <CONFIG_HAS_MCG>` && \ :option:`SOC_FAMILY_KINETIS <CONFIG_SOC_FAMILY_KINETIS>`)

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- 5
- 5
- 5
- 0

Kconfig definitions
===================

.. highlight:: kconfig

At ``boards/arm/frdm_kl25z/Kconfig.defconfig:20``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18``

Menu path: (Top)

.. parsed-literal::

    config MCG_FRDIV
    	int
    	default 5
    	depends on \ :option:`BOARD_FRDM_KL25Z <CONFIG_BOARD_FRDM_KL25Z>`

----

At ``boards/arm/frdm_kw41z/Kconfig.defconfig:14``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18``

Menu path: (Top)

.. parsed-literal::

    config MCG_FRDIV
    	int
    	default 5
    	depends on \ :option:`BOARD_FRDM_KW41Z <CONFIG_BOARD_FRDM_KW41Z>`

----

At ``boards/arm/hexiwear_kw40z/Kconfig.defconfig:14``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18``

Menu path: (Top)

.. parsed-literal::

    config MCG_FRDIV
    	int
    	default 5
    	depends on \ :option:`BOARD_HEXIWEAR_KW40Z <CONFIG_BOARD_HEXIWEAR_KW40Z>`

----

At ``soc/arm/nxp_kinetis/Kconfig:94``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:28`` → ``soc/Kconfig:11`` → ``/home/runner/work/bridle/bridle/workspace/build/Kconfig/Kconfig.soc.arch:2``

Menu path: (Top) → Hardware Configuration

.. parsed-literal::

    config MCG_FRDIV
    	int "FLL external reference divider"
    	range 0 7
    	default 0
    	depends on \ :option:`HAS_MCG <CONFIG_HAS_MCG>` && \ :option:`SOC_FAMILY_KINETIS <CONFIG_SOC_FAMILY_KINETIS>`
    	help
    	  Selects the amount to divide down the external reference clock for the
    	  FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
    	  kHz.

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*