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.. dtcompatible:: st,stm32l4-pll-clock
.. _dtbinding_st_stm32l4_pll_clock:

st,stm32l4-pll-clock
####################

Vendor: :ref:`STMicroelectronics <dt_vendor_st>`

Description
***********



.. code-block:: none

   PLL node binding for STM32L4 and STM32L5 devices

   It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
   Only main PLL is supported for now.

   These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
   an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
   clock in this acceptable range.

   Each PLL can have up to 3 output clocks and for each output clock, the
   frequency can be computed with the following formulae:

     f(PLL_P) = f(VCO clock) / PLLP  --> PLLSAI3CLK
     f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48M1CLK
     f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)

       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

   The PLL output frequency must not exceed 80 MHz.

Properties
**********

.. tabs::

   .. group-tab:: Node specific properties

      Properties not inherited from the base binding file.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``#clock-cells``
           - ``int``
           - .. code-block:: none

                Number of items to expect in a Clock specifier


             This property is **required**.

         * - ``div-m``
           - ``int``
           - .. code-block:: none

                Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
                input clock
                Valid range: 1 - 8



             This property is **required**.

         * - ``mul-n``
           - ``int``
           - .. code-block:: none

                Main PLL multiplication factor for VCO
                Valid range: 8 - 86



             This property is **required**.

         * - ``div-p``
           - ``int``
           - .. code-block:: none

                Main PLL division factor for PLLSAI3CLK



             Legal values: ``7``, ``17``

         * - ``div-q``
           - ``int``
           - .. code-block:: none

                Main PLL division factor for PLL48M1CLK (48 MHz clock).



             Legal values: ``2``, ``4``, ``6``, ``8``

         * - ``div-r``
           - ``int``
           - .. code-block:: none

                Main PLL division factor for PLLCLK (system clock)



             This property is **required**.

             Legal values: ``2``, ``4``, ``6``, ``8``



   .. group-tab:: Deprecated node specific properties

      Deprecated properties not inherited from the base binding file.

      (None)

   .. group-tab:: Base properties

      Properties inherited from the base binding file, which defines
      common properties that may be set on many nodes. Not all of these
      may apply to the "st,stm32l4-pll-clock" compatible.

      .. list-table::
         :widths: 1 1 4
         :header-rows: 1

         * - Name
           - Type
           - Details

         * - ``clocks``
           - ``phandle-array``
           - .. code-block:: none

                Clock gate information


             This property is **required**.

         * - ``status``
           - ``string``
           - .. code-block:: none

                indicates the operational status of a device


             Legal values: ``'ok'``, ``'okay'``, ``'disabled'``, ``'reserved'``, ``'fail'``, ``'fail-sss'``

             See :ref:`zephyr:dt-important-props` for more information.

         * - ``compatible``
           - ``string-array``
           - .. code-block:: none

                compatible strings


             This property is **required**.

             See :ref:`zephyr:dt-important-props` for more information.

         * - ``reg``
           - ``array``
           - .. code-block:: none

                register space


             See :ref:`zephyr:dt-important-props` for more information.

         * - ``reg-names``
           - ``string-array``
           - .. code-block:: none

                name of each register space


         * - ``interrupts``
           - ``array``
           - .. code-block:: none

                interrupts for device


             See :ref:`zephyr:dt-important-props` for more information.

         * - ``interrupts-extended``
           - ``compound``
           - .. code-block:: none

                extended interrupt specifier for device


         * - ``interrupt-names``
           - ``string-array``
           - .. code-block:: none

                name of each interrupt


         * - ``interrupt-parent``
           - ``phandle``
           - .. code-block:: none

                phandle to interrupt controller node


         * - ``label``
           - ``string``
           - .. code-block:: none

                Human readable string describing the device (used as device_get_binding() argument)


             See :ref:`zephyr:dt-important-props` for more information.

         * - ``clock-names``
           - ``string-array``
           - .. code-block:: none

                name of each clock


         * - ``#address-cells``
           - ``int``
           - .. code-block:: none

                number of address cells in reg property


         * - ``#size-cells``
           - ``int``
           - .. code-block:: none

                number of size cells in reg property


         * - ``dmas``
           - ``phandle-array``
           - .. code-block:: none

                DMA channels specifiers


         * - ``dma-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of DMA channel specifiers


         * - ``io-channels``
           - ``phandle-array``
           - .. code-block:: none

                IO channels specifiers


         * - ``io-channel-names``
           - ``string-array``
           - .. code-block:: none

                Provided names of IO channel specifiers