:orphan:

.. title:: CLOCK_NPCX_OSC_CYCLES_PER_SEC

.. option:: CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC

*CDCG PLL frequency*

Type: ``int``

Help
====

.. code-block:: none

    Core Domain Clock (OSC_CLK) Generator PLL frequency,
    allowed values: From 10Mhz to 100Mhz.

Direct dependencies
===================

\ :option:`SOC_FAMILY_NPCX <CONFIG_SOC_FAMILY_NPCX>` && \ :option:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`

*(Includes any dependencies from ifs and menus.)*

Default
=======

- 48000000

Kconfig definition
==================



At ``<Zephyr Driver>/clock_control/Kconfig.npcx:12``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:32`` → ``<Zephyr Driver>/Kconfig:54`` → ``<Zephyr Driver>/clock_control/Kconfig:43``

Menu path: (Top) → Device Drivers → Hardware clock controller support

.. code-block:: kconfig

    config CLOCK_NPCX_OSC_CYCLES_PER_SEC
    	int "CDCG PLL frequency"
    	range 10000000 100000000
    	default 48000000
    	depends on SOC_FAMILY_NPCX && CLOCK_CONTROL
    	help
    	  Core Domain Clock (OSC_CLK) Generator PLL frequency,
    	  allowed values: From 10Mhz to 100Mhz.

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*