:orphan: .. title:: CONFIG_2ND_LVL_INTR_00_OFFSET .. kconfig:: CONFIG_2ND_LVL_INTR_00_OFFSET CONFIG_2ND_LVL_INTR_00_OFFSET ############################# *Level 1 IRQ line for 2ND level aggregator 0* Type: ``int`` Help ==== .. code-block:: none This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). Direct dependencies =================== \ :kconfig:`BOARD_INTEL_ADSP_CAVS15 ` || \ :kconfig:`BOARD_INTEL_ADSP_CAVS18 ` || \ :kconfig:`BOARD_INTEL_ADSP_CAVS20 ` || \ :kconfig:`BOARD_INTEL_ADSP_CAVS25 ` || \ :kconfig:`BOARD_INTEL_S1000_CRB ` || (\ :kconfig:`MULTI_LEVEL_INTERRUPTS ` && \ :kconfig:`SOC_OPENISA_RV32M1_RISCV32 `) || \ :kconfig:`SOC_SERIES_RISCV_ANDES_V5 ` || \ :kconfig:`SOC_SERIES_RISCV32_MIV ` || \ :kconfig:`SOC_SERIES_RISCV_SIFIVE_FREEDOM ` || \ :kconfig:`SOC_SERIES_STARFIVE_JH71XX ` || \ :kconfig:`SOC_SERIES_RISCV_VIRT ` || (\ :kconfig:`MULTI_LEVEL_INTERRUPTS ` && \ :kconfig:`SOC_OPENISA_RV32M1_RISCV32 `) || \ :kconfig:`SOC_SERIES_RISCV_ANDES_V5 ` || \ :kconfig:`SOC_SERIES_RISCV32_MIV ` || \ :kconfig:`SOC_SERIES_RISCV_SIFIVE_FREEDOM ` || \ :kconfig:`SOC_SERIES_STARFIVE_JH71XX ` || \ :kconfig:`SOC_SERIES_RISCV_VIRT ` || \ :kconfig:`2ND_LEVEL_INTERRUPTS ` *(Includes any dependencies from ifs and menus.)* Defaults ======== - \ :kconfig:`CAVS_ICTL_0_OFFSET ` - \ :kconfig:`CAVS_ICTL_0_OFFSET ` - \ :kconfig:`CAVS_ICTL_0_OFFSET ` - \ :kconfig:`CAVS_ICTL_0_OFFSET ` - \ :kconfig:`CAVS_ICTL_0_OFFSET ` - 24 - 11 - 11 - 11 - 11 - 11 - 24 - 11 - 11 - 11 - 11 - 11 - 0 Kconfig definitions =================== At ``/xtensa/intel_adsp_cavs15/Kconfig.defconfig:19`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:22`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default CAVS_ICTL_0_OFFSET depends on BOARD_INTEL_ADSP_CAVS15 ---- At ``/xtensa/intel_adsp_cavs18/Kconfig.defconfig:19`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:22`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default CAVS_ICTL_0_OFFSET depends on BOARD_INTEL_ADSP_CAVS18 ---- At ``/xtensa/intel_adsp_cavs20/Kconfig.defconfig:19`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:22`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default CAVS_ICTL_0_OFFSET depends on BOARD_INTEL_ADSP_CAVS20 ---- At ``/xtensa/intel_adsp_cavs25/Kconfig.defconfig:19`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:22`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default CAVS_ICTL_0_OFFSET depends on BOARD_INTEL_ADSP_CAVS25 ---- At ``/xtensa/intel_s1000_crb/Kconfig.defconfig:21`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:22`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default CAVS_ICTL_0_OFFSET depends on BOARD_INTEL_S1000_CRB ---- At ``/riscv/openisa_rv32m1/Kconfig.defconfig:65`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``/kconfig/Kconfig.soc.defconfig:1`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 24 depends on MULTI_LEVEL_INTERRUPTS && SOC_OPENISA_RV32M1_RISCV32 ---- At ``/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:39`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``/kconfig/Kconfig.soc.defconfig:1`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_RISCV_ANDES_V5 ---- At ``/riscv/riscv-privilege/miv/Kconfig.defconfig.series:26`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``/kconfig/Kconfig.soc.defconfig:1`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_RISCV32_MIV ---- At ``/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:26`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``/kconfig/Kconfig.soc.defconfig:1`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM ---- At ``/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:27`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``/kconfig/Kconfig.soc.defconfig:1`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_STARFIVE_JH71XX ---- At ``/riscv/riscv-privilege/virt/Kconfig.defconfig.series:27`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``/kconfig/Kconfig.soc.defconfig:1`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_RISCV_VIRT ---- At ``/riscv/openisa_rv32m1/Kconfig.defconfig:65`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 24 depends on MULTI_LEVEL_INTERRUPTS && SOC_OPENISA_RV32M1_RISCV32 ---- At ``/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:39`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_RISCV_ANDES_V5 ---- At ``/riscv/riscv-privilege/miv/Kconfig.defconfig.series:26`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_RISCV32_MIV ---- At ``/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:26`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM ---- At ``/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:27`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_STARFIVE_JH71XX ---- At ``/riscv/riscv-privilege/virt/Kconfig.defconfig.series:27`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``/riscv/riscv-privilege/Kconfig.defconfig:6`` Menu path: (Top) .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int default 11 depends on SOC_SERIES_RISCV_VIRT ---- At ``/interrupt_controller/Kconfig.multilevel.aggregator_template:3`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:28`` → ``/interrupt_controller/Kconfig:48`` → ``/interrupt_controller/Kconfig.multilevel:59`` Menu path: (Top) → Device Drivers → Interrupt Controllers → Multi-level interrupt support → Second-level interrupt support .. code-block:: kconfig config 2ND_LVL_INTR_00_OFFSET int "Level 1 IRQ line for 2ND level aggregator 0" default 0 depends on 2ND_LEVEL_INTERRUPTS help This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). *(The 'depends on' condition includes propagated dependencies from ifs and menus.)*