:orphan:

.. title:: CONFIG_CAVS_TIMER

.. kconfig:: CONFIG_CAVS_TIMER

CONFIG_CAVS_TIMER
#################

*CAVS DSP Wall Clock Timer on Intel SoC*

Type: ``bool``

Help
====

.. code-block:: none

    The DSP wall clock timer is a timer driven directly by
    external oscillator and is external to the CPU core(s).
    It is not as fast as the internal core clock, but provides
    a common and synchronized counter for all CPU cores (which
    is useful for SMP).

Direct dependencies
===================

\ :kconfig:`SOC_SERIES_INTEL_CAVS_V15 <CONFIG_SOC_SERIES_INTEL_CAVS_V15>` || \ :kconfig:`SOC_SERIES_INTEL_CAVS_V18 <CONFIG_SOC_SERIES_INTEL_CAVS_V18>` || \ :kconfig:`SOC_SERIES_INTEL_CAVS_V20 <CONFIG_SOC_SERIES_INTEL_CAVS_V20>` || \ :kconfig:`SOC_SERIES_INTEL_CAVS_V25 <CONFIG_SOC_SERIES_INTEL_CAVS_V25>` || (\ :kconfig:`SMP <CONFIG_SMP>` && \ :kconfig:`SOC_INTEL_S1000 <CONFIG_SOC_INTEL_S1000>`) || \ :kconfig:`SOC_SERIES_INTEL_CAVS_V15 <CONFIG_SOC_SERIES_INTEL_CAVS_V15>` || \ :kconfig:`SOC_SERIES_INTEL_CAVS_V18 <CONFIG_SOC_SERIES_INTEL_CAVS_V18>` || \ :kconfig:`SOC_SERIES_INTEL_CAVS_V20 <CONFIG_SOC_SERIES_INTEL_CAVS_V20>` || \ :kconfig:`SOC_SERIES_INTEL_CAVS_V25 <CONFIG_SOC_SERIES_INTEL_CAVS_V25>` || (\ :kconfig:`SMP <CONFIG_SMP>` && \ :kconfig:`SOC_INTEL_S1000 <CONFIG_SOC_INTEL_S1000>`) || \ :kconfig:`CAVS_ICTL <CONFIG_CAVS_ICTL>`

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- y
- y
- y
- y
- y
- y
- y
- y
- y
- y

Symbols selected by this symbol
===============================

- \ :kconfig:`TICKLESS_CAPABLE <CONFIG_TICKLESS_CAPABLE>`

Kconfig definitions
===================



At ``<Zephyr SoC>/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series:24``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/xtensa/intel_adsp/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SOC_SERIES_INTEL_CAVS_V15

----

At ``<Zephyr SoC>/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series:24``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/xtensa/intel_adsp/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SOC_SERIES_INTEL_CAVS_V18

----

At ``<Zephyr SoC>/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series:24``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/xtensa/intel_adsp/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SOC_SERIES_INTEL_CAVS_V20

----

At ``<Zephyr SoC>/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series:28``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/xtensa/intel_adsp/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SOC_SERIES_INTEL_CAVS_V25

----

At ``<Zephyr SoC>/xtensa/intel_s1000/Kconfig.defconfig:42``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SMP && SOC_INTEL_S1000

----

At ``<Zephyr SoC>/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series:24``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/xtensa/intel_adsp/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SOC_SERIES_INTEL_CAVS_V15

----

At ``<Zephyr SoC>/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series:24``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/xtensa/intel_adsp/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SOC_SERIES_INTEL_CAVS_V18

----

At ``<Zephyr SoC>/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series:24``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/xtensa/intel_adsp/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SOC_SERIES_INTEL_CAVS_V20

----

At ``<Zephyr SoC>/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series:28``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/xtensa/intel_adsp/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SOC_SERIES_INTEL_CAVS_V25

----

At ``<Zephyr SoC>/xtensa/intel_s1000/Kconfig.defconfig:42``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27``

Menu path: (Top)

.. code-block:: kconfig

    config CAVS_TIMER
    	bool
    	default y
    	depends on SMP && SOC_INTEL_S1000

----

At ``<Zephyr Driver>/timer/Kconfig:327``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``<Zephyr Driver>/Kconfig:30``

Menu path: (Top) → Device Drivers → Timer Drivers

.. code-block:: kconfig

    config CAVS_TIMER
    	bool "CAVS DSP Wall Clock Timer on Intel SoC"
    	select TICKLESS_CAPABLE
    	depends on CAVS_ICTL
    	help
    	  The DSP wall clock timer is a timer driven directly by
    	  external oscillator and is external to the CPU core(s).
    	  It is not as fast as the internal core clock, but provides
    	  a common and synchronized counter for all CPU cores (which
    	  is useful for SMP).

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*