:orphan: .. title:: CONFIG_CLOCK_STM32_PLL_M_DIVISOR .. kconfig:: CONFIG_CLOCK_STM32_PLL_M_DIVISOR CONFIG_CLOCK_STM32_PLL_M_DIVISOR ################################ *Division factor for PLL VCO input clock* *PLL divisor* *PLL divisor* *PLL divisor* *PLL divisor* Type: ``int`` Help ==== .. code-block:: none PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 Help ==== .. code-block:: none PLL divisor, allowed values: 0-63. Help ==== .. code-block:: none PLL divisor, L4: allowed values: 1-8. PLL VCO input ranges from 4 to 16MHz L5: allowed values: 1-16. PLL VCO input ranges from 4 to 16MHz WB: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz WL: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz Help ==== .. code-block:: none PLL divisor, allowed values: 1-8. Help ==== .. code-block:: none PLL divisor, allowed values: 1-16. Direct dependencies =================== (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :kconfig:`SOC_SERIES_STM32F2X ` || \ :kconfig:`SOC_SERIES_STM32F4X ` || \ :kconfig:`SOC_SERIES_STM32F7X `) && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :kconfig:`SOC_SERIES_STM32H7X ` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :kconfig:`SOC_SERIES_STM32L4X ` || \ :kconfig:`SOC_SERIES_STM32L5X ` || \ :kconfig:`SOC_SERIES_STM32WBX ` || \ :kconfig:`SOC_SERIES_STM32WLX `) && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :kconfig:`SOC_SERIES_STM32G0X ` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :kconfig:`SOC_SERIES_STM32G4X ` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) *(Includes any dependencies from ifs and menus.)* Defaults ======== - 8 - 32 - 1 - 1 - 4 Kconfig definitions =================== At ``/clock_control/Kconfig.stm32f2_f4_f7:8`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:152`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_M_DIVISOR int "Division factor for PLL VCO input clock" range 2 63 default 8 depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F2X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 ---- At ``/clock_control/Kconfig.stm32h7:67`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:153`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 0 63 default 32 depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLL divisor, allowed values: 0-63. ---- At ``/clock_control/Kconfig.stm32l4_l5_wb_wl:8`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:155`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 8 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX range 1 16 if SOC_SERIES_STM32L5X default 1 depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX) && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLL divisor, L4: allowed values: 1-8. PLL VCO input ranges from 4 to 16MHz L5: allowed values: 1-16. PLL VCO input ranges from 4 to 16MHz WB: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz WL: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz ---- At ``/clock_control/Kconfig.stm32g0:17`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:156`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 8 default 1 depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G0X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLL divisor, allowed values: 1-8. ---- At ``/clock_control/Kconfig.stm32g4:8`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:157`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 16 default 4 depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G4X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLL divisor, allowed values: 1-16. *(The 'depends on' condition includes propagated dependencies from ifs and menus.)*