:orphan: .. title:: CONFIG_CLOCK_STM32_PLL_P_DIVISOR .. kconfig:: CONFIG_CLOCK_STM32_PLL_P_DIVISOR CONFIG_CLOCK_STM32_PLL_P_DIVISOR ################################ *PLL division factor for main system clock* *PLL P Divisor* *PLL P Divisor* *PLL P Divisor* *PLL P Divisor* Type: ``int`` Help ==== .. code-block:: none PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8 Help ==== .. code-block:: none PLL P Output divisor, allowed values: 1-128. Help ==== .. code-block:: none PLL P Output divisor L4: allowed values: 0, 7, 17. PLLP do not exceed 80MHz L5: allowed values: 0, 7, 17. PLLP do not exceed 80MHz WB: allowed values: 0, 2-32. PLLP do not exceed 64MHz WL: allowed values: 0, 2-32. PLLP do not exceed 48MHz Help ==== .. code-block:: none PLL P VCO divisor, allowed values: 2-32. Help ==== .. code-block:: none PLL P Output divisor, allowed values: 7, 17. Direct dependencies =================== (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :kconfig:`SOC_SERIES_STM32F2X ` || \ :kconfig:`SOC_SERIES_STM32F4X ` || \ :kconfig:`SOC_SERIES_STM32F7X `) && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :kconfig:`SOC_SERIES_STM32H7X ` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && (\ :kconfig:`SOC_SERIES_STM32L4X ` || \ :kconfig:`SOC_SERIES_STM32L5X ` || \ :kconfig:`SOC_SERIES_STM32WBX ` || \ :kconfig:`SOC_SERIES_STM32WLX `) && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :kconfig:`SOC_SERIES_STM32G0X ` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL ` && \ :kconfig:`SOC_SERIES_STM32G4X ` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS ` && !\ :kconfig:`SOC_SERIES_STM32MP1X ` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE ` && \ :kconfig:`CLOCK_CONTROL `) *(Includes any dependencies from ifs and menus.)* Defaults ======== - 4 - 2 - 7 - 2 - 7 Kconfig definitions =================== At ``/clock_control/Kconfig.stm32f2_f4_f7:31`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:152`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_P_DIVISOR int "PLL division factor for main system clock" range 2 8 default 4 depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F2X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8 ---- At ``/clock_control/Kconfig.stm32h7:83`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:153`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 1 128 default 2 depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLL P Output divisor, allowed values: 1-128. ---- At ``/clock_control/Kconfig.stm32l4_l5_wb_wl:34`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:155`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 0 17 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X range 0 32 if SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX default 7 depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX) && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLL P Output divisor L4: allowed values: 0, 7, 17. PLLP do not exceed 80MHz L5: allowed values: 0, 7, 17. PLLP do not exceed 80MHz WB: allowed values: 0, 2-32. PLLP do not exceed 64MHz WL: allowed values: 0, 2-32. PLLP do not exceed 48MHz ---- At ``/clock_control/Kconfig.stm32g0:25`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:156`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 2 32 default 2 depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G0X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLL P VCO divisor, allowed values: 2-32. ---- At ``/clock_control/Kconfig.stm32g4:24`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``/Kconfig:56`` → ``/clock_control/Kconfig:25`` → ``/clock_control/Kconfig.stm32:157`` Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control .. code-block:: kconfig config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 7 17 default 7 depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G4X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL help PLL P Output divisor, allowed values: 7, 17. *(The 'depends on' condition includes propagated dependencies from ifs and menus.)*