:orphan:

.. title:: CONFIG_CLOCK_STM32_PLL_R_DIVISOR

.. kconfig:: CONFIG_CLOCK_STM32_PLL_R_DIVISOR

CONFIG_CLOCK_STM32_PLL_R_DIVISOR
################################

*PLL R Divisor*

*PLL R Divisor*

*PLL R Divisor*

*PLL R Divisor*

Type: ``int``

Help
====

.. code-block:: none

    PLL R Output divisor, allowed values: 1-128.

Help
====

.. code-block:: none

    PLL R Output divisor
    L4: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 80MHz
    L5: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 110MHz
    WB: allowed values: 0, 2-8. PLLR do not exceed 64MHz
    WL: allowed values: 0, 2-8. PLLR do not exceed 48MHz

Help
====

.. code-block:: none

    PLL R VCO divisor, allowed values: 2-8.

Help
====

.. code-block:: none

    PLL R Output divisor, allowed values: 2, 4, 6, 8.

Direct dependencies
===================

(\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL <CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL>` && \ :kconfig:`SOC_SERIES_STM32H7X <CONFIG_SOC_SERIES_STM32H7X>` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS <CONFIG_CLOCK_CONTROL_STM32_HAS_DTS>` && !\ :kconfig:`SOC_SERIES_STM32MP1X <CONFIG_SOC_SERIES_STM32MP1X>` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE <CONFIG_CLOCK_CONTROL_STM32_CUBE>` && \ :kconfig:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL <CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL>` && (\ :kconfig:`SOC_SERIES_STM32L4X <CONFIG_SOC_SERIES_STM32L4X>` || \ :kconfig:`SOC_SERIES_STM32L5X <CONFIG_SOC_SERIES_STM32L5X>` || \ :kconfig:`SOC_SERIES_STM32WBX <CONFIG_SOC_SERIES_STM32WBX>` || \ :kconfig:`SOC_SERIES_STM32WLX <CONFIG_SOC_SERIES_STM32WLX>`) && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS <CONFIG_CLOCK_CONTROL_STM32_HAS_DTS>` && !\ :kconfig:`SOC_SERIES_STM32MP1X <CONFIG_SOC_SERIES_STM32MP1X>` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE <CONFIG_CLOCK_CONTROL_STM32_CUBE>` && \ :kconfig:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL <CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL>` && \ :kconfig:`SOC_SERIES_STM32G0X <CONFIG_SOC_SERIES_STM32G0X>` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS <CONFIG_CLOCK_CONTROL_STM32_HAS_DTS>` && !\ :kconfig:`SOC_SERIES_STM32MP1X <CONFIG_SOC_SERIES_STM32MP1X>` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE <CONFIG_CLOCK_CONTROL_STM32_CUBE>` && \ :kconfig:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`) || (\ :kconfig:`CLOCK_STM32_SYSCLK_SRC_PLL <CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL>` && \ :kconfig:`SOC_SERIES_STM32G4X <CONFIG_SOC_SERIES_STM32G4X>` && !\ :kconfig:`CLOCK_CONTROL_STM32_HAS_DTS <CONFIG_CLOCK_CONTROL_STM32_HAS_DTS>` && !\ :kconfig:`SOC_SERIES_STM32MP1X <CONFIG_SOC_SERIES_STM32MP1X>` && \ :kconfig:`CLOCK_CONTROL_STM32_CUBE <CONFIG_CLOCK_CONTROL_STM32_CUBE>` && \ :kconfig:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`)

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- 2
- 4
- 2
- 2

Kconfig definitions
===================



At ``<Zephyr Driver>/clock_control/Kconfig.stm32h7:99``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``<Zephyr Driver>/Kconfig:56`` → ``<Zephyr Driver>/clock_control/Kconfig:25`` → ``<Zephyr Driver>/clock_control/Kconfig.stm32:153``

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

.. code-block:: kconfig

    config CLOCK_STM32_PLL_R_DIVISOR
    	int "PLL R Divisor"
    	range 1 128
    	default 2
    	depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    	help
    	  PLL R Output divisor, allowed values: 1-128.

----

At ``<Zephyr Driver>/clock_control/Kconfig.stm32l4_l5_wb_wl:59``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``<Zephyr Driver>/Kconfig:56`` → ``<Zephyr Driver>/clock_control/Kconfig:25`` → ``<Zephyr Driver>/clock_control/Kconfig.stm32:155``

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

.. code-block:: kconfig

    config CLOCK_STM32_PLL_R_DIVISOR
    	int "PLL R Divisor"
    	range 0 8
    	default 4
    	depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX) && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    	help
    	  PLL R Output divisor
    	  L4: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 80MHz
    	  L5: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 110MHz
    	  WB: allowed values: 0, 2-8. PLLR do not exceed 64MHz
    	  WL: allowed values: 0, 2-8. PLLR do not exceed 48MHz

----

At ``<Zephyr Driver>/clock_control/Kconfig.stm32g0:43``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``<Zephyr Driver>/Kconfig:56`` → ``<Zephyr Driver>/clock_control/Kconfig:25`` → ``<Zephyr Driver>/clock_control/Kconfig.stm32:156``

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

.. code-block:: kconfig

    config CLOCK_STM32_PLL_R_DIVISOR
    	int "PLL R Divisor"
    	range 2 8
    	default 2
    	depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G0X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    	help
    	  PLL R VCO divisor, allowed values: 2-8.

----

At ``<Zephyr Driver>/clock_control/Kconfig.stm32g4:40``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``<Zephyr Driver>/Kconfig:56`` → ``<Zephyr Driver>/clock_control/Kconfig:25`` → ``<Zephyr Driver>/clock_control/Kconfig.stm32:157``

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

.. code-block:: kconfig

    config CLOCK_STM32_PLL_R_DIVISOR
    	int "PLL R Divisor"
    	range 2 8
    	default 2
    	depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G4X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    	help
    	  PLL R Output divisor, allowed values: 2, 4, 6, 8.

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*