:orphan:

.. title:: CONFIG_CLOCK_STM32_PLL_SRC_PLL2

.. kconfig:: CONFIG_CLOCK_STM32_PLL_SRC_PLL2

CONFIG_CLOCK_STM32_PLL_SRC_PLL2
###############################

*PLL2*

Type: ``bool``

Help
====

.. code-block:: none

    Use PLL2 as source of main PLL. This is equivalent of defining
    PLL2 as source PREDIV1SCR. If not selected, default source is HSE.

Direct dependencies
===================

\ :kconfig:`SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE <CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE>` && \ :ref:`<choice: STM32 PLL Clock Source> <choice_317>`

*(Includes any dependencies from ifs and menus.)*

Kconfig definition
==================



At ``<Zephyr Driver>/clock_control/Kconfig.stm32:132``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``<Zephyr Driver>/Kconfig:56`` → ``<Zephyr Driver>/clock_control/Kconfig:25``

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control → STM32 PLL Clock Source

.. code-block:: kconfig

    config CLOCK_STM32_PLL_SRC_PLL2
    	bool "PLL2"
    	depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && <choice>
    	help
    	  Use PLL2 as source of main PLL. This is equivalent of defining
    	  PLL2 as source PREDIV1SCR. If not selected, default source is HSE.

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*