:orphan:

.. title:: CONFIG_I2S_STM32_PLLI2S_PLLM

.. kconfig:: CONFIG_I2S_STM32_PLLI2S_PLLM

CONFIG_I2S_STM32_PLLI2S_PLLM
############################

*Division factor for PLLI2S VCO input clock*

Type: ``int``

Help
====

.. code-block:: none

    Division factor for the audio PLL (PLLI2S) VCO input clock.
    PLLM factor should be selected to ensure that the VCO
    input frequency ranges from 1 to 2 MHz. It is recommended
    to select a frequency of 2 MHz to limit PLL jitter.
    Allowed values: 2-63

Direct dependencies
===================

(\ :kconfig:`I2S <CONFIG_I2S>` && \ :kconfig:`BOARD_NUCLEO_F411RE <CONFIG_BOARD_NUCLEO_F411RE>`) || (\ :kconfig:`I2S <CONFIG_I2S>` && \ :kconfig:`BOARD_NUCLEO_F411RE <CONFIG_BOARD_NUCLEO_F411RE>`) || (\ :kconfig:`I2S <CONFIG_I2S>` && \ :kconfig:`BOARD_96B_ARGONKEY <CONFIG_BOARD_96B_ARGONKEY>`) || (\ :kconfig:`I2S <CONFIG_I2S>` && \ :kconfig:`BOARD_96B_STM32_SENSOR_MEZ <CONFIG_BOARD_96B_STM32_SENSOR_MEZ>`) || (\ :kconfig:`I2S <CONFIG_I2S>` && \ :kconfig:`BOARD_NUCLEO_F411RE <CONFIG_BOARD_NUCLEO_F411RE>`) || (\ :kconfig:`I2S_STM32_USE_PLLI2S_ENABLE <CONFIG_I2S_STM32_USE_PLLI2S_ENABLE>` && \ :kconfig:`I2S_STM32 <CONFIG_I2S_STM32>` && \ :kconfig:`I2S <CONFIG_I2S>`)

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- 8
- 8
- 8
- 8
- 8
- 8

Kconfig definitions
===================



At ``<Zephyr Boards>/shields/x_nucleo_iks02a1/boards/nucleo_f411re.defconfig:34``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:18`` → ``<BuildDir>/kconfig/Kconfig.shield.defconfig:1`` → ``<Zephyr Boards>/shields/x_nucleo_iks02a1/Kconfig.defconfig:5``

Menu path: (Top)

.. code-block:: kconfig

    config I2S_STM32_PLLI2S_PLLM
    	int
    	default 8
    	depends on I2S && BOARD_NUCLEO_F411RE

----

At ``<Zephyr Boards>/shields/x_nucleo_iks02a1/boards/nucleo_f411re.defconfig:34``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:20`` → ``<Zephyr Boards>/shields/x_nucleo_iks02a1/Kconfig.defconfig:5``

Menu path: (Top)

.. code-block:: kconfig

    config I2S_STM32_PLLI2S_PLLM
    	int
    	default 8
    	depends on I2S && BOARD_NUCLEO_F411RE

----

At ``<Zephyr Boards>/arm/96b_argonkey/Kconfig.defconfig:17``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:22``

Menu path: (Top)

.. code-block:: kconfig

    config I2S_STM32_PLLI2S_PLLM
    	int
    	default 8
    	depends on I2S && BOARD_96B_ARGONKEY

----

At ``<Zephyr Boards>/arm/96b_stm32_sensor_mez/Kconfig.defconfig:17``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:22``

Menu path: (Top)

.. code-block:: kconfig

    config I2S_STM32_PLLI2S_PLLM
    	int
    	default 8
    	depends on I2S && BOARD_96B_STM32_SENSOR_MEZ

----

At ``<Zephyr Boards>/shields/x_nucleo_iks02a1/boards/nucleo_f411re.defconfig:34``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:22`` → ``<Zephyr Boards>/shields/x_nucleo_iks02a1/Kconfig.defconfig:5``

Menu path: (Top)

.. code-block:: kconfig

    config I2S_STM32_PLLI2S_PLLM
    	int
    	default 8
    	depends on I2S && BOARD_NUCLEO_F411RE

----

At ``<Zephyr Driver>/i2s/Kconfig.stm32:30``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:42`` → ``<Zephyr Driver>/Kconfig:44`` → ``<Zephyr Driver>/i2s/Kconfig:28``

Menu path: (Top) → Device Drivers → I2S bus drivers → STM32 MCU I2S controller driver → Enable usage of PLL

.. code-block:: kconfig

    config I2S_STM32_PLLI2S_PLLM
    	int "Division factor for PLLI2S VCO input clock"
    	range 2 63
    	default 8
    	depends on I2S_STM32_USE_PLLI2S_ENABLE && I2S_STM32 && I2S
    	help
    	  Division factor for the audio PLL (PLLI2S) VCO input clock.
    	  PLLM factor should be selected to ensure that the VCO
    	  input frequency ranges from 1 to 2 MHz. It is recommended
    	  to select a frequency of 2 MHz to limit PLL jitter.
    	  Allowed values: 2-63

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*