:orphan:

.. title:: CONFIG_PICO_PSRAM_CS_IO

.. kconfig:: CONFIG_PICO_PSRAM_CS_IO

CONFIG_PICO_PSRAM_CS_IO
#######################

*PSRAM CS IO number*

*PSRAM CS IO number*

Type: ``int``

Help
====

.. code-block:: none

    The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.

    For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
    IO.
    For the reference hardware design, please refer to
    https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf

Help
====

.. code-block:: none

    The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.

    For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
    IO.
    For the reference hardware design, please refer to
    https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf

Direct dependencies
===================

(\ :kconfig:`ESP_SPIRAM <CONFIG_ESP_SPIRAM>` && \ :kconfig:`SOC_ESP32 <CONFIG_SOC_ESP32>` && \ :ref:`<choice: SoC/CPU/Configuration Selection> <choice_41>`) || (\ :kconfig:`ESP_SPIRAM <CONFIG_ESP_SPIRAM>` && \ :kconfig:`SOC_ESP32 <CONFIG_SOC_ESP32>` && \ :ref:`<choice: SoC/CPU/Configuration Selection> <choice_41>`)

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- 10
- 10

Kconfig definitions
===================



At ``<Zephyr SoC>/xtensa/esp32/Kconfig.soc:152``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:7`` → ``<BuildDir>/kconfig/Kconfig.soc:1``

Menu path: (Top) → SoC/CPU/Configuration Selection → ESP32 → Support for external, SPI-connected RAM → SPI RAM config → PSRAM clock and cs IO for ESP32-PICO

.. code-block:: kconfig

    config PICO_PSRAM_CS_IO
    	int "PSRAM CS IO number"
    	range 0 33
    	default 10
    	depends on ESP_SPIRAM && SOC_ESP32 && <choice>
    	help
    	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
	  
    	  For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
    	  IO.
    	  For the reference hardware design, please refer to
    	  https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf

----

At ``<Zephyr SoC>/xtensa/esp32/Kconfig.soc:152``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:9``

Menu path: (Top) → SoC/CPU/Configuration Selection → ESP32 → Support for external, SPI-connected RAM → SPI RAM config → PSRAM clock and cs IO for ESP32-PICO

.. code-block:: kconfig

    config PICO_PSRAM_CS_IO
    	int "PSRAM CS IO number"
    	range 0 33
    	default 10
    	depends on ESP_SPIRAM && SOC_ESP32 && <choice>
    	help
    	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
	  
    	  For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
    	  IO.
    	  For the reference hardware design, please refer to
    	  https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*