:orphan:

.. title:: CONFIG_RISCV_HAS_PLIC

.. kconfig:: CONFIG_RISCV_HAS_PLIC

CONFIG_RISCV_HAS_PLIC
#####################

*Does the SOC provide support for a Platform Level Interrupt Controller*

*Does the SOC provide support for a Platform Level Interrupt Controller*

Type: ``bool``

Help
====

.. code-block:: none

    Does the SOC provide support for a Platform Level Interrupt Controller

Help
====

.. code-block:: none

    Does the SOC provide support for a Platform Level Interrupt Controller

Direct dependencies
===================

\ :kconfig:`SOC_RISCV32_LITEX_VEXRISCV <CONFIG_SOC_RISCV32_LITEX_VEXRISCV>` || \ :kconfig:`SOC_SERIES_RISCV_ANDES_V5 <CONFIG_SOC_SERIES_RISCV_ANDES_V5>` || \ :kconfig:`SOC_SERIES_RISCV32_MIV <CONFIG_SOC_SERIES_RISCV32_MIV>` || \ :kconfig:`SOC_SERIES_RISCV_SIFIVE_FREEDOM <CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM>` || \ :kconfig:`SOC_SERIES_STARFIVE_JH71XX <CONFIG_SOC_SERIES_STARFIVE_JH71XX>` || \ :kconfig:`SOC_SERIES_RISCV_TELINK_B91 <CONFIG_SOC_SERIES_RISCV_TELINK_B91>` || \ :kconfig:`SOC_SERIES_RISCV_VIRT <CONFIG_SOC_SERIES_RISCV_VIRT>` || \ :kconfig:`SOC_RISCV32_LITEX_VEXRISCV <CONFIG_SOC_RISCV32_LITEX_VEXRISCV>` || \ :kconfig:`SOC_SERIES_RISCV_ANDES_V5 <CONFIG_SOC_SERIES_RISCV_ANDES_V5>` || \ :kconfig:`SOC_SERIES_RISCV32_MIV <CONFIG_SOC_SERIES_RISCV32_MIV>` || \ :kconfig:`SOC_SERIES_RISCV_SIFIVE_FREEDOM <CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM>` || \ :kconfig:`SOC_SERIES_STARFIVE_JH71XX <CONFIG_SOC_SERIES_STARFIVE_JH71XX>` || \ :kconfig:`SOC_SERIES_RISCV_TELINK_B91 <CONFIG_SOC_SERIES_RISCV_TELINK_B91>` || \ :kconfig:`SOC_SERIES_RISCV_VIRT <CONFIG_SOC_SERIES_RISCV_VIRT>` || \ :kconfig:`SOC_FAMILY_RISCV_PRIVILEGE <CONFIG_SOC_FAMILY_RISCV_PRIVILEGE>` || \ :kconfig:`SOC_FAMILY_RISCV_PRIVILEGE <CONFIG_SOC_FAMILY_RISCV_PRIVILEGE>`

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- y
- y
- y
- y
- y
- y
- y
- y
- y
- y
- y
- y

Kconfig definitions
===================



At ``<Zephyr SoC>/riscv/litex-vexriscv/Kconfig.defconfig:15``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	depends on SOC_RISCV32_LITEX_VEXRISCV

----

At ``<Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:30``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_ANDES_V5

----

At ``<Zephyr SoC>/riscv/riscv-privilege/miv/Kconfig.defconfig.series:17``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV32_MIV

----

At ``<Zephyr SoC>/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:17``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

----

At ``<Zephyr SoC>/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:18``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_STARFIVE_JH71XX

----

At ``<Zephyr SoC>/riscv/riscv-privilege/telink_b91/Kconfig.defconfig.series:22``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_TELINK_B91

----

At ``<Zephyr SoC>/riscv/riscv-privilege/virt/Kconfig.defconfig.series:18``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_VIRT

----

At ``<Zephyr SoC>/riscv/litex-vexriscv/Kconfig.defconfig:15``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	depends on SOC_RISCV32_LITEX_VEXRISCV

----

At ``<Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:30``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_ANDES_V5

----

At ``<Zephyr SoC>/riscv/riscv-privilege/miv/Kconfig.defconfig.series:17``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV32_MIV

----

At ``<Zephyr SoC>/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:17``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

----

At ``<Zephyr SoC>/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:18``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_STARFIVE_JH71XX

----

At ``<Zephyr SoC>/riscv/riscv-privilege/telink_b91/Kconfig.defconfig.series:22``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_TELINK_B91

----

At ``<Zephyr SoC>/riscv/riscv-privilege/virt/Kconfig.defconfig.series:18``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_VIRT

----

At ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig:15``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:15`` → ``<BuildDir>/kconfig/Kconfig.soc.arch:2``

Menu path: (Top) → Hardware Configuration

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool "Does the SOC provide support for a Platform Level Interrupt Controller"
    	depends on SOC_FAMILY_RISCV_PRIVILEGE
    	help
    	  Does the SOC provide support for a Platform Level Interrupt Controller

----

At ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig:15``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:18``

Menu path: (Top) → Hardware Configuration

.. code-block:: kconfig

    config RISCV_HAS_PLIC
    	bool "Does the SOC provide support for a Platform Level Interrupt Controller"
    	depends on SOC_FAMILY_RISCV_PRIVILEGE
    	help
    	  Does the SOC provide support for a Platform Level Interrupt Controller

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*