:orphan:

.. title:: CONFIG_RISCV_SOC_INTERRUPT_INIT

.. kconfig:: CONFIG_RISCV_SOC_INTERRUPT_INIT

CONFIG_RISCV_SOC_INTERRUPT_INIT
###############################

*Enable SOC-based interrupt initialization*

Type: ``bool``

Help
====

.. code-block:: none

    Enable SOC-based interrupt initialization
    (call soc_interrupt_init, within _IntLibInit when enabled)

Direct dependencies
===================

\ :kconfig:`SOC_OPENISA_RV32M1_RISCV32 <CONFIG_SOC_OPENISA_RV32M1_RISCV32>` || \ :kconfig:`SOC_SERIES_RISCV_ANDES_V5 <CONFIG_SOC_SERIES_RISCV_ANDES_V5>` || \ :kconfig:`SOC_SERIES_RISCV32_MIV <CONFIG_SOC_SERIES_RISCV32_MIV>` || \ :kconfig:`SOC_SERIES_RISCV_SIFIVE_FREEDOM <CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM>` || \ :kconfig:`SOC_SERIES_STARFIVE_JH71XX <CONFIG_SOC_SERIES_STARFIVE_JH71XX>` || \ :kconfig:`SOC_SERIES_RISCV_TELINK_B91 <CONFIG_SOC_SERIES_RISCV_TELINK_B91>` || \ :kconfig:`SOC_SERIES_RISCV_VIRT <CONFIG_SOC_SERIES_RISCV_VIRT>` || \ :kconfig:`SOC_OPENISA_RV32M1_RISCV32 <CONFIG_SOC_OPENISA_RV32M1_RISCV32>` || \ :kconfig:`SOC_SERIES_RISCV_ANDES_V5 <CONFIG_SOC_SERIES_RISCV_ANDES_V5>` || \ :kconfig:`SOC_SERIES_RISCV32_MIV <CONFIG_SOC_SERIES_RISCV32_MIV>` || \ :kconfig:`SOC_SERIES_RISCV_SIFIVE_FREEDOM <CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM>` || \ :kconfig:`SOC_SERIES_STARFIVE_JH71XX <CONFIG_SOC_SERIES_STARFIVE_JH71XX>` || \ :kconfig:`SOC_SERIES_RISCV_TELINK_B91 <CONFIG_SOC_SERIES_RISCV_TELINK_B91>` || \ :kconfig:`SOC_SERIES_RISCV_VIRT <CONFIG_SOC_SERIES_RISCV_VIRT>` || \ :kconfig:`RISCV <CONFIG_RISCV>`

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- y
- y
- y
- y
- y
- y
- y
- y
- y
- y
- y
- y
- y
- y

Symbols that select this symbol
===============================

- \ :kconfig:`SOC_OPENISA_RV32M1_RISCV32 <CONFIG_SOC_OPENISA_RV32M1_RISCV32>`
- \ :kconfig:`SOC_OPENISA_RV32M1_RISCV32 <CONFIG_SOC_OPENISA_RV32M1_RISCV32>`

Kconfig definitions
===================



At ``<Zephyr SoC>/riscv/openisa_rv32m1/Kconfig.defconfig:33``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_OPENISA_RV32M1_RISCV32

----

At ``<Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:24``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_ANDES_V5

----

At ``<Zephyr SoC>/riscv/riscv-privilege/miv/Kconfig.defconfig.series:11``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV32_MIV

----

At ``<Zephyr SoC>/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:11``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

----

At ``<Zephyr SoC>/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:12``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_STARFIVE_JH71XX

----

At ``<Zephyr SoC>/riscv/riscv-privilege/telink_b91/Kconfig.defconfig.series:14``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_TELINK_B91

----

At ``<Zephyr SoC>/riscv/riscv-privilege/virt/Kconfig.defconfig.series:12``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:25`` → ``<BuildDir>/kconfig/Kconfig.soc.defconfig:1`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_VIRT

----

At ``<Zephyr SoC>/riscv/openisa_rv32m1/Kconfig.defconfig:33``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_OPENISA_RV32M1_RISCV32

----

At ``<Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:24``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_ANDES_V5

----

At ``<Zephyr SoC>/riscv/riscv-privilege/miv/Kconfig.defconfig.series:11``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV32_MIV

----

At ``<Zephyr SoC>/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:11``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

----

At ``<Zephyr SoC>/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:12``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_STARFIVE_JH71XX

----

At ``<Zephyr SoC>/riscv/riscv-privilege/telink_b91/Kconfig.defconfig.series:14``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_TELINK_B91

----

At ``<Zephyr SoC>/riscv/riscv-privilege/virt/Kconfig.defconfig.series:12``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:27`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6``

Menu path: (Top)

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool
    	default y
    	depends on SOC_SERIES_RISCV_VIRT

----

At ``<Zephyr Architecture>/riscv/Kconfig:99``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:39`` → ``<Zephyr Architecture>/Kconfig:12``

Menu path: (Top) → RISCV Options → RISCV Processor Options

.. code-block:: kconfig

    config RISCV_SOC_INTERRUPT_INIT
    	bool "Enable SOC-based interrupt initialization"
    	depends on RISCV
    	help
    	  Enable SOC-based interrupt initialization
    	  (call soc_interrupt_init, within _IntLibInit when enabled)

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*