:orphan:

.. title:: CONFIG_SOC_ANDES_V5_PMA

.. kconfig:: CONFIG_SOC_ANDES_V5_PMA

CONFIG_SOC_ANDES_V5_PMA
#######################

*Enable Andes V5 Physical Memory Attribute (PMA)*

*Enable Andes V5 Physical Memory Attribute (PMA)*

Type: ``bool``

Help
====

.. code-block:: none

    This option enables the Andes V5 PMA, in order to support SW to
    configure physical memory attribute by PMA CSRs. The address
    matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
    (power-of-two alignment).

Help
====

.. code-block:: none

    This option enables the Andes V5 PMA, in order to support SW to
    configure physical memory attribute by PMA CSRs. The address
    matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
    (power-of-two alignment).

Direct dependencies
===================

\ :kconfig:`SOC_SERIES_RISCV_ANDES_V5 <CONFIG_SOC_SERIES_RISCV_ANDES_V5>` || \ :kconfig:`SOC_SERIES_RISCV_ANDES_V5 <CONFIG_SOC_SERIES_RISCV_ANDES_V5>`

*(Includes any dependencies from ifs and menus.)*

Defaults
========

No defaults. Implicitly defaults to ``n``.

Symbols selected by this symbol
===============================

- \ :kconfig:`ARCH_HAS_NOCACHE_MEMORY_SUPPORT <CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT>`
- \ :kconfig:`ARCH_HAS_NOCACHE_MEMORY_SUPPORT <CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT>`

Kconfig definitions
===================



At ``<Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.soc:72``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:15`` → ``<BuildDir>/kconfig/Kconfig.soc.arch:2`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig:22``

Menu path: (Top) → Hardware Configuration

.. code-block:: kconfig

    config SOC_ANDES_V5_PMA
    	bool "Enable Andes V5 Physical Memory Attribute (PMA)"
    	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
    	depends on SOC_SERIES_RISCV_ANDES_V5
    	help
    	  This option enables the Andes V5 PMA, in order to support SW to
    	  configure physical memory attribute by PMA CSRs. The address
    	  matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
    	  (power-of-two alignment).

----

At ``<Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.soc:72``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:18`` → ``<Zephyr SoC>/riscv/riscv-privilege/Kconfig:22``

Menu path: (Top) → Hardware Configuration

.. code-block:: kconfig

    config SOC_ANDES_V5_PMA
    	bool "Enable Andes V5 Physical Memory Attribute (PMA)"
    	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
    	depends on SOC_SERIES_RISCV_ANDES_V5
    	help
    	  This option enables the Andes V5 PMA, in order to support SW to
    	  configure physical memory attribute by PMA CSRs. The address
    	  matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
    	  (power-of-two alignment).

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*