:orphan:

.. title:: CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA

.. kconfig:: CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA

CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA
#################################

*PLL DIVA*

*PLL DIVA*

Type: ``int``

Help
====

.. code-block:: none

    This is the divider DIVA used by the PLL.
    The processor clock is (MAINCK * (MULA + 1) / DIVA).

    Board config file can override this settings
    for a particular board.

    Setting DIVA=0 would disable PLL at boot, this is currently
    not supported.

    With default of MULA == 24, and DIVA == 1,
    PLL is running at 25 times the main clock frequency.

Help
====

.. code-block:: none

    This is the divider DIVA used by the PLL.
    The processor clock is (MAINCK * (MULA + 1) / DIVA).

    Board config file can override this settings
    for a particular board.

    Setting DIVA=0 would disable PLL at boot, this is currently
    not supported.

    With default of MULA == 24, and DIVA == 1,
    PLL is running at 25 times the main clock frequency.

Direct dependencies
===================

(\ :kconfig:`SOC_SERIES_SAME70 <CONFIG_SOC_SERIES_SAME70>` && \ :kconfig:`SOC_FAMILY_SAM <CONFIG_SOC_FAMILY_SAM>`) || (\ :kconfig:`SOC_SERIES_SAME70 <CONFIG_SOC_SERIES_SAME70>` && \ :kconfig:`SOC_FAMILY_SAM <CONFIG_SOC_FAMILY_SAM>`)

*(Includes any dependencies from ifs and menus.)*

Defaults
========

- 1
- 1

Kconfig definitions
===================



At ``<Zephyr SoC>/arm/atmel_sam/same70/Kconfig.soc:133``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:15`` → ``<BuildDir>/kconfig/Kconfig.soc.arch:2`` → ``<Zephyr SoC>/arm/atmel_sam/Kconfig:17``

Menu path: (Top) → Hardware Configuration

.. code-block:: kconfig

    config SOC_ATMEL_SAME70_PLLA_DIVA
    	int "PLL DIVA"
    	range 1 255
    	default 1
    	depends on SOC_SERIES_SAME70 && SOC_FAMILY_SAM
    	help
    	  This is the divider DIVA used by the PLL.
    	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
	  
    	  Board config file can override this settings
    	  for a particular board.
	  
    	  Setting DIVA=0 would disable PLL at boot, this is currently
    	  not supported.
	  
    	  With default of MULA == 24, and DIVA == 1,
    	  PLL is running at 25 times the main clock frequency.

----

At ``<Zephyr SoC>/arm/atmel_sam/same70/Kconfig.soc:133``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:18`` → ``<Zephyr SoC>/arm/atmel_sam/Kconfig:17``

Menu path: (Top) → Hardware Configuration

.. code-block:: kconfig

    config SOC_ATMEL_SAME70_PLLA_DIVA
    	int "PLL DIVA"
    	range 1 255
    	default 1
    	depends on SOC_SERIES_SAME70 && SOC_FAMILY_SAM
    	help
    	  This is the divider DIVA used by the PLL.
    	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
	  
    	  Board config file can override this settings
    	  for a particular board.
	  
    	  Setting DIVA=0 would disable PLL at boot, this is currently
    	  not supported.
	  
    	  With default of MULA == 24, and DIVA == 1,
    	  PLL is running at 25 times the main clock frequency.

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*