:orphan:

.. title:: CONFIG_SOC_OPENISA_RV32M1_RISCV32

.. kconfig:: CONFIG_SOC_OPENISA_RV32M1_RISCV32

CONFIG_SOC_OPENISA_RV32M1_RISCV32
#################################

*OpenISA RV32M1 RISC-V cores*

*OpenISA RV32M1 RISC-V cores*

Type: ``bool``

Help
====

.. code-block:: none

    Enable support for OpenISA RV32M1 RISC-V processors. Choose
    this option to target the RI5CY or ZERO-RISCY core. This
    option should not be used to target either Arm core.

Help
====

.. code-block:: none

    Enable support for OpenISA RV32M1 RISC-V processors. Choose
    this option to target the RI5CY or ZERO-RISCY core. This
    option should not be used to target either Arm core.

Direct dependencies
===================

\ :ref:`<choice: SoC/CPU/Configuration Selection> <choice_41>` || \ :ref:`<choice: SoC/CPU/Configuration Selection> <choice_41>`

*(Includes any dependencies from ifs and menus.)*

Symbols selected by this symbol
===============================

- \ :kconfig:`RISCV <CONFIG_RISCV>`
- \ :kconfig:`XIP <CONFIG_XIP>`
- \ :kconfig:`HAS_RV32M1_LPUART <CONFIG_HAS_RV32M1_LPUART>`
- \ :kconfig:`HAS_RV32M1_LPI2C <CONFIG_HAS_RV32M1_LPI2C>`
- \ :kconfig:`HAS_RV32M1_LPSPI <CONFIG_HAS_RV32M1_LPSPI>`
- \ :kconfig:`HAS_RV32M1_TPM <CONFIG_HAS_RV32M1_TPM>`
- \ :kconfig:`ATOMIC_OPERATIONS_C <CONFIG_ATOMIC_OPERATIONS_C>`
- \ :kconfig:`VEGA_SDK_HAL <CONFIG_VEGA_SDK_HAL>`
- \ :kconfig:`RISCV_SOC_INTERRUPT_INIT <CONFIG_RISCV_SOC_INTERRUPT_INIT>`
- \ :kconfig:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`
- \ :kconfig:`HAS_RV32M1_FTFX <CONFIG_HAS_RV32M1_FTFX>`
- \ :kconfig:`HAS_FLASH_LOAD_OFFSET <CONFIG_HAS_FLASH_LOAD_OFFSET>`
- \ :kconfig:`BUILD_OUTPUT_HEX <CONFIG_BUILD_OUTPUT_HEX>`
- \ :kconfig:`RISCV <CONFIG_RISCV>`
- \ :kconfig:`XIP <CONFIG_XIP>`
- \ :kconfig:`HAS_RV32M1_LPUART <CONFIG_HAS_RV32M1_LPUART>`
- \ :kconfig:`HAS_RV32M1_LPI2C <CONFIG_HAS_RV32M1_LPI2C>`
- \ :kconfig:`HAS_RV32M1_LPSPI <CONFIG_HAS_RV32M1_LPSPI>`
- \ :kconfig:`HAS_RV32M1_TPM <CONFIG_HAS_RV32M1_TPM>`
- \ :kconfig:`ATOMIC_OPERATIONS_C <CONFIG_ATOMIC_OPERATIONS_C>`
- \ :kconfig:`VEGA_SDK_HAL <CONFIG_VEGA_SDK_HAL>`
- \ :kconfig:`RISCV_SOC_INTERRUPT_INIT <CONFIG_RISCV_SOC_INTERRUPT_INIT>`
- \ :kconfig:`CLOCK_CONTROL <CONFIG_CLOCK_CONTROL>`
- \ :kconfig:`HAS_RV32M1_FTFX <CONFIG_HAS_RV32M1_FTFX>`
- \ :kconfig:`HAS_FLASH_LOAD_OFFSET <CONFIG_HAS_FLASH_LOAD_OFFSET>`
- \ :kconfig:`BUILD_OUTPUT_HEX <CONFIG_BUILD_OUTPUT_HEX>`

Kconfig definitions
===================



At ``<Zephyr SoC>/riscv/openisa_rv32m1/Kconfig.soc:4``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:7`` → ``<BuildDir>/kconfig/Kconfig.soc:1``

Menu path: (Top) → SoC/CPU/Configuration Selection

.. code-block:: kconfig

    config SOC_OPENISA_RV32M1_RISCV32
    	bool "OpenISA RV32M1 RISC-V cores"
    	select RISCV
    	select XIP
    	select HAS_RV32M1_LPUART
    	select HAS_RV32M1_LPI2C
    	select HAS_RV32M1_LPSPI
    	select HAS_RV32M1_TPM
    	select ATOMIC_OPERATIONS_C
    	select VEGA_SDK_HAL
    	select RISCV_SOC_INTERRUPT_INIT
    	select CLOCK_CONTROL
    	select HAS_RV32M1_FTFX
    	select HAS_FLASH_LOAD_OFFSET
    	select BUILD_OUTPUT_HEX
    	depends on <choice>
    	help
    	  Enable support for OpenISA RV32M1 RISC-V processors. Choose
    	  this option to target the RI5CY or ZERO-RISCY core. This
    	  option should not be used to target either Arm core.

----

At ``<Zephyr SoC>/riscv/openisa_rv32m1/Kconfig.soc:4``

Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``<Zephyr SoC>/Kconfig:9``

Menu path: (Top) → SoC/CPU/Configuration Selection

.. code-block:: kconfig

    config SOC_OPENISA_RV32M1_RISCV32
    	bool "OpenISA RV32M1 RISC-V cores"
    	select RISCV
    	select XIP
    	select HAS_RV32M1_LPUART
    	select HAS_RV32M1_LPI2C
    	select HAS_RV32M1_LPSPI
    	select HAS_RV32M1_TPM
    	select ATOMIC_OPERATIONS_C
    	select VEGA_SDK_HAL
    	select RISCV_SOC_INTERRUPT_INIT
    	select CLOCK_CONTROL
    	select HAS_RV32M1_FTFX
    	select HAS_FLASH_LOAD_OFFSET
    	select BUILD_OUTPUT_HEX
    	depends on <choice>
    	help
    	  Enable support for OpenISA RV32M1 RISC-V processors. Choose
    	  this option to target the RI5CY or ZERO-RISCY core. This
    	  option should not be used to target either Arm core.

*(The 'depends on' condition includes propagated dependencies from ifs and menus.)*