:orphan: .. title:: CONFIG_SOC_SERIES_NEORV32 .. kconfig:: CONFIG_SOC_SERIES_NEORV32 CONFIG_SOC_SERIES_NEORV32 ######################### *NEORV32 Processor* Type: ``bool`` Help ==== .. code-block:: none Enable support for the NEORV32 Processor (SoC). The NEORV32 CPU implementation must have the following RISC-V ISA extensions enabled in order to support Zephyr: - M (Integer Multiplication and Division) - Zicsr (Control and Status Register (CSR) Instructions) The following NEORV32 CPU ISA extensions are not currently supported by Zephyr and can safely be disabled: - A (Atomic Instructions) - E (Embedded, only 16 integer registers) - Zbb (Basic Bit Manipulation) - Zfinx (Floating Point in Integer Registers) Direct dependencies =================== \ :ref:` ` *(Includes any dependencies from ifs and menus.)* Symbols selected by this symbol =============================== - \ :kconfig:`RISCV ` - \ :kconfig:`SOC_FAMILY_RISCV_PRIVILEGE ` Kconfig definition ================== At ``/riscv/riscv-privilege/neorv32/Kconfig.series:4`` Included via ``Kconfig:8`` → ``Kconfig.zephyr:38`` → ``/Kconfig:9`` → ``/riscv/riscv-privilege/Kconfig.soc:6`` Menu path: (Top) → SoC/CPU/Configuration Selection .. code-block:: kconfig config SOC_SERIES_NEORV32 bool "NEORV32 Processor" select RISCV select SOC_FAMILY_RISCV_PRIVILEGE depends on help Enable support for the NEORV32 Processor (SoC). The NEORV32 CPU implementation must have the following RISC-V ISA extensions enabled in order to support Zephyr: - M (Integer Multiplication and Division) - Zicsr (Control and Status Register (CSR) Instructions) The following NEORV32 CPU ISA extensions are not currently supported by Zephyr and can safely be disabled: - A (Atomic Instructions) - E (Embedded, only 16 integer registers) - Zbb (Basic Bit Manipulation) - Zfinx (Floating Point in Integer Registers) *(The 'depends on' condition includes propagated dependencies from ifs and menus.)*