Zephyr Project API  3.1.0
A Scalable Open Source RTOS
stm32_clock_control.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2016 BayLibre, SAS
4 * Copyright (c) 2017-2022 Linaro Limited.
5 * Copyright (c) 2017 RnDity Sp. z o.o.
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
10#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11
12#include <zephyr/drivers/clock_control.h>
13
14#if defined(CONFIG_SOC_SERIES_STM32F0X)
15#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
16#elif defined(CONFIG_SOC_SERIES_STM32F1X)
17#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
18#elif defined(CONFIG_SOC_SERIES_STM32F3X)
19#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
20#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
21 defined(CONFIG_SOC_SERIES_STM32F4X) || \
22 defined(CONFIG_SOC_SERIES_STM32F7X)
23#include <zephyr/dt-bindings/clock/stm32f4_clock.h>
24#elif defined(CONFIG_SOC_SERIES_STM32G0X)
25#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
26#elif defined(CONFIG_SOC_SERIES_STM32G4X)
27#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
28#elif defined(CONFIG_SOC_SERIES_STM32L0X)
29#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
30#elif defined(CONFIG_SOC_SERIES_STM32L1X)
31#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
32#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
33 defined(CONFIG_SOC_SERIES_STM32L5X)
34#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
35#elif defined(CONFIG_SOC_SERIES_STM32WBX)
36#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
37#elif defined(CONFIG_SOC_SERIES_STM32WLX)
38#include <zephyr/dt-bindings/clock/stm32wl_clock.h>
39#elif defined(CONFIG_SOC_SERIES_STM32H7X)
40#include <zephyr/dt-bindings/clock/stm32h7_clock.h>
41#elif defined(CONFIG_SOC_SERIES_STM32U5X)
42#include <zephyr/dt-bindings/clock/stm32u5_clock.h>
43#else
44#include <zephyr/dt-bindings/clock/stm32_clock.h>
45#endif
46
48#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
49
52#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
53#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
54#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
55#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
56#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
57#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
58#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
59#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
60
61#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler)
62#define STM32_CORE_PRESCALER STM32_AHB_PRESCALER
63#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
64#define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER
65#endif
66
67#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
68#define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER
69#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
70#define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER
71#else
72#define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER
73#endif
74
75#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
76#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
77#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
78#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
79#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
80#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
81
82#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
83
84/* To enable use of IS_ENABLED utility macro, these symbols
85 * should not be defined directly using DT_SAME_NODE.
86 */
87#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
88#define STM32_SYSCLK_SRC_PLL 1
89#endif
90#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
91#define STM32_SYSCLK_SRC_HSI 1
92#endif
93#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
94#define STM32_SYSCLK_SRC_HSE 1
95#endif
96#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
97#define STM32_SYSCLK_SRC_MSI 1
98#endif
99#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
100#define STM32_SYSCLK_SRC_MSIS 1
101#endif
102#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
103#define STM32_SYSCLK_SRC_CSI 1
104#endif
105
106
109#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
110 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
111 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
112 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
113 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
114 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
115 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
116 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
117 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
118#define STM32_PLL_ENABLED 1
119#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
120#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
121#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
122#define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
123#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
124#define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
125#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
126#define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
127#endif
128
129#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay)
130#define STM32_PLL3_ENABLED 1
131#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
132#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
133#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
134#define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
135#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
136#define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
137#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
138#define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
139#endif
140
141#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
142#define STM32_PLL_ENABLED 1
143#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
144#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
145#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
146 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
147 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
148#define STM32_PLL_ENABLED 1
149#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
150#define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv)
151#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
152#define STM32_PLL_ENABLED 1
153#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
154#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
155#endif
156
157#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) && \
158 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
159#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
160#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
161#define STM32_PLL_SRC_MSI 1
162#endif
163#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
164#define STM32_PLL_SRC_MSIS 1
165#endif
166#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
167#define STM32_PLL_SRC_HSI 1
168#endif
169#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
170#define STM32_PLL_SRC_CSI 1
171#endif
172#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
173#define STM32_PLL_SRC_HSE 1
174#endif
175#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
176#define STM32_PLL_SRC_PLL2 1
177#endif
178
179#endif
180
181
184#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
185#define STM32_LSE_ENABLED 1
186#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
187#define STM32_LSE_DRIVING 0
188#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
189#define STM32_LSE_ENABLED 1
190#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
191#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
192#else
193#define STM32_LSE_ENABLED 0
194#define STM32_LSE_FREQ 0
195#define STM32_LSE_DRIVING 0
196#endif
197
198#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
199 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
200#define STM32_MSI_ENABLED 1
201#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
202#endif
203
204#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
205#define STM32_MSI_ENABLED 1
206#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
207#endif
208
209#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
210#define STM32_MSIS_ENABLED 1
211#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
212#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
213#else
214#define STM32_MSIS_ENABLED 0
215#define STM32_MSIS_RANGE 0
216#define STM32_MSIS_PLL_MODE 0
217#endif
218
219#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay)
220#define STM32_MSIK_ENABLED 1
221#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
222#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
223#else
224#define STM32_MSIK_ENABLED 0
225#define STM32_MSIK_RANGE 0
226#define STM32_MSIK_PLL_MODE 0
227#endif
228
229#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
230#define STM32_CSI_ENABLED 1
231#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
232#else
233#define STM32_CSI_FREQ 0
234#endif
235
236#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
237#define STM32_LSI_ENABLED 1
238#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
239#else
240#define STM32_LSI_FREQ 0
241#endif
242
243#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay)
244#define STM32_HSI_ENABLED 1
245#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
246#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay)
247#define STM32_HSI_ENABLED 1
248#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
249#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
250#else
251#define STM32_HSI_DIVISOR 1
252#define STM32_HSI_FREQ 0
253#endif
254
255#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay)
256#define STM32_HSE_ENABLED 1
257#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
258#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
259#define STM32_HSE_ENABLED 1
260#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
261#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
262#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
263#define STM32_HSE_ENABLED 1
264#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
265#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
266#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
267#else
268#define STM32_HSE_FREQ 0
269#endif
270
271#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay)
272#define STM32_CKPER_ENABLED 1
273#endif
274
277struct stm32_pclken {
278 uint32_t bus;
279 uint32_t enr;
280};
281
284#define STM32_CLOCK_INFO(clk_index, id) \
285 { \
286 .enr = DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(id), clk_index, bits),\
287 .bus = DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(id), clk_index, bus) \
288 }
289#define STM32_DT_CLOCKS(id) \
290 { \
291 LISTIFY(DT_NUM_CLOCKS(DT_NODELABEL(id)), \
292 STM32_CLOCK_INFO, (,), id) \
293 }
294
295#define STM32_INST_CLOCK_INFO(clk_index, inst) \
296 { \
297 .enr = DT_INST_CLOCKS_CELL_BY_IDX(inst, clk_index, bits), \
298 .bus = DT_INST_CLOCKS_CELL_BY_IDX(inst, clk_index, bus) \
299 }
300#define STM32_DT_INST_CLOCKS(inst) \
301 { \
302 LISTIFY(DT_INST_NUM_CLOCKS(inst), \
303 STM32_INST_CLOCK_INFO, (,), inst) \
304 }
305
306#define STM32_OPT_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
307#define STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT \
308 (DT_INST_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_INST_SUPPORT) 0)
309
310#define STM32_OPT_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
311#define STM32_DT_DEV_OPT_CLOCK_SUPPORT \
312 (DT_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_SUPPORT) 0)
313
321#define STM32_CLOCK_REG_GET(clock) \
322 (((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK)
323
329#define STM32_CLOCK_SHIFT_GET(clock) \
330 (((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK)
331
337#define STM32_CLOCK_MASK_GET(clock) \
338 (((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK)
339
345#define STM32_CLOCK_VAL_GET(clock) \
346 (((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK)
347
348#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
clock_control.h
Public Clock Control APIs.
uint32_t
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
stm32_clock.h
stm32f0_clock.h
stm32f1_clock.h
stm32f3_clock.h
stm32f4_clock.h
stm32g0_clock.h
stm32g4_clock.h
stm32h7_clock.h
stm32l0_clock.h
stm32l1_clock.h
stm32l4_clock.h
stm32u5_clock.h
stm32wb_clock.h
stm32wl_clock.h
stm32_pclken
Definition: stm32_clock_control.h:277
stm32_pclken::bus
uint32_t bus
Definition: stm32_clock_control.h:278
stm32_pclken::enr
uint32_t enr
Definition: stm32_clock_control.h:279