Zephyr Project API  3.2.0
A Scalable Open Source RTOS
arch.h
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1/*
2 * Copyright (c) 2014 Wind River Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
16#ifndef ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_
17#define ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_
18
19#include <zephyr/devicetree.h>
20#include <zephyr/sw_isr_table.h>
24#include "sys-io-common.h"
25
34
35#ifdef CONFIG_ARC_CONNECT
37#endif
38
39#ifdef CONFIG_ISA_ARCV2
40#include "v2/sys_io.h"
41#ifdef CONFIG_ARC_HAS_SECURE
43#endif
44#endif
45
46#if defined(CONFIG_ARC_FIRQ) && defined(CONFIG_ISA_ARCV3)
47#error "Unsupported configuration: ARC_FIRQ and ISA_ARCV3"
48#endif
49
50/*
51 * We don't allow the configuration with FIRQ enabled and only one interrupt priority level
52 * (so all interrupts are FIRQ). Such configuration isn't supported in software and it is not
53 * beneficial from the performance point of view.
54 */
55#if defined(CONFIG_ARC_FIRQ) && CONFIG_NUM_IRQ_PRIO_LEVELS < 2
56#error "Unsupported configuration: ARC_FIRQ and (NUM_IRQ_PRIO_LEVELS < 2)"
57#endif
58
59#if CONFIG_RGF_NUM_BANKS > 1 && !defined(CONFIG_ARC_FIRQ)
60#error "Unsupported configuration: (RGF_NUM_BANKS > 1) and !ARC_FIRQ"
61#endif
62
63/*
64 * It's required to have more than one interrupt priority level to use second register bank
65 * - otherwise all interrupts will use same register bank. Such configuration isn't supported in
66 * software and it is not beneficial from the performance point of view.
67 */
68#if CONFIG_RGF_NUM_BANKS > 1 && CONFIG_NUM_IRQ_PRIO_LEVELS < 2
69#error "Unsupported configuration: (RGF_NUM_BANKS > 1) and (NUM_IRQ_PRIO_LEVELS < 2)"
70#endif
71
72#if defined(CONFIG_ARC_FIRQ_STACK) && !defined(CONFIG_ARC_FIRQ)
73#error "Unsupported configuration: ARC_FIRQ_STACK and !ARC_FIRQ"
74#endif
75
76#if defined(CONFIG_ARC_FIRQ_STACK) && CONFIG_RGF_NUM_BANKS < 2
77#error "Unsupported configuration: ARC_FIRQ_STACK and (RGF_NUM_BANKS < 2)"
78#endif
79
80#if defined(CONFIG_SMP) && !defined(CONFIG_MULTITHREADING)
81#error "Non-multithreading mode isn't supported on SMP targets"
82#endif
83
84#ifndef _ASMLANGUAGE
85
86#ifdef __cplusplus
87extern "C" {
88#endif
89
90#ifdef CONFIG_64BIT
91#define ARCH_STACK_PTR_ALIGN 8
92#else
93#define ARCH_STACK_PTR_ALIGN 4
94#endif /* CONFIG_64BIT */
95
96BUILD_ASSERT(CONFIG_ISR_STACK_SIZE % ARCH_STACK_PTR_ALIGN == 0,
97 "CONFIG_ISR_STACK_SIZE must be a multiple of ARCH_STACK_PTR_ALIGN");
98
99BUILD_ASSERT(CONFIG_ARC_EXCEPTION_STACK_SIZE % ARCH_STACK_PTR_ALIGN == 0,
100 "CONFIG_ARC_EXCEPTION_STACK_SIZE must be a multiple of ARCH_STACK_PTR_ALIGN");
101
102/* Indicate, for a minimally sized MPU region, how large it must be and what
103 * its base address must be aligned to.
104 *
105 * For regions that are NOT the minimum size, this define has no semantics
106 * on ARC MPUv2 as its regions must be power of two size and aligned to their
107 * own size. On ARC MPUv4, region sizes are arbitrary and this just indicates
108 * the required size granularity.
109 */
110#ifdef CONFIG_ARC_CORE_MPU
111#if CONFIG_ARC_MPU_VER == 2
112#define Z_ARC_MPU_ALIGN 2048
113#elif (CONFIG_ARC_MPU_VER == 3) || (CONFIG_ARC_MPU_VER == 4) || (CONFIG_ARC_MPU_VER == 6)
114#define Z_ARC_MPU_ALIGN 32
115#else
116#error "Unsupported MPU version"
117#endif
118#endif
119
120#ifdef CONFIG_MPU_STACK_GUARD
121#define Z_ARC_STACK_GUARD_SIZE Z_ARC_MPU_ALIGN
122#else
123#define Z_ARC_STACK_GUARD_SIZE 0
124#endif
125
126/* Kernel-only stacks have the following layout if a stack guard is enabled:
127 *
128 * +------------+ <- thread.stack_obj
129 * | Guard | } Z_ARC_STACK_GUARD_SIZE
130 * +------------+ <- thread.stack_info.start
131 * | Kernel |
132 * | stack |
133 * | |
134 * +............|
135 * | TLS | } thread.stack_info.delta
136 * +------------+ <- thread.stack_info.start + thread.stack_info.size
137 */
138#ifdef CONFIG_MPU_STACK_GUARD
139#define ARCH_KERNEL_STACK_RESERVED Z_ARC_STACK_GUARD_SIZE
140#define ARCH_KERNEL_STACK_OBJ_ALIGN Z_ARC_MPU_ALIGN
141#endif
142
143#ifdef CONFIG_USERSPACE
144/* Any thread running In user mode will have full access to the region denoted
145 * by thread.stack_info.
146 *
147 * Thread-local storage is at the very highest memory locations of this area.
148 * Memory for TLS and any initial random stack pointer offset is captured
149 * in thread.stack_info.delta.
150 */
151#ifdef CONFIG_MPU_STACK_GUARD
152/* MPU guards are only supported with V3 MPU and later. In this configuration
153 * the stack object will contain the MPU guard, the privilege stack, and then
154 * the stack buffer in that order:
155 *
156 * +------------+ <- thread.stack_obj
157 * | Guard | } Z_ARC_STACK_GUARD_SIZE
158 * +------------+ <- thread.arch.priv_stack_start
159 * | Priv Stack | } CONFIG_PRIVILEGED_STACK_SIZE
160 * +------------+ <- thread.stack_info.start
161 * | Thread |
162 * | stack |
163 * | |
164 * +............|
165 * | TLS | } thread.stack_info.delta
166 * +------------+ <- thread.stack_info.start + thread.stack_info.size
167 */
168#define ARCH_THREAD_STACK_RESERVED (Z_ARC_STACK_GUARD_SIZE + \
169 CONFIG_PRIVILEGED_STACK_SIZE)
170#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
171/* We need to be able to exactly cover the stack buffer with an MPU region,
172 * so round its size up to the required granularity of the MPU
173 */
174#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
175 (ROUND_UP((size), Z_ARC_MPU_ALIGN))
176BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
177 "improper privilege stack size");
178#else /* !CONFIG_MPU_STACK_GUARD */
179/* Userspace enabled, but supervisor stack guards are not in use */
180#ifdef CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
181/* Use defaults for everything. The privilege elevation stack is located
182 * in another area of memory generated at build time by gen_kobject_list.py
183 *
184 * +------------+ <- thread.arch.priv_stack_start
185 * | Priv Stack | } Z_KERNEL_STACK_LEN(CONFIG_PRIVILEGED_STACK_SIZE)
186 * +------------+
187 *
188 * +------------+ <- thread.stack_obj = thread.stack_info.start
189 * | Thread |
190 * | stack |
191 * | |
192 * +............|
193 * | TLS | } thread.stack_info.delta
194 * +------------+ <- thread.stack_info.start + thread.stack_info.size
195 */
196#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
197 Z_POW2_CEIL(ROUND_UP((size), Z_ARC_MPU_ALIGN))
198#define ARCH_THREAD_STACK_OBJ_ALIGN(size) \
199 ARCH_THREAD_STACK_SIZE_ADJUST(size)
200#define ARCH_THREAD_STACK_RESERVED 0
201#else /* !CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT */
202/* Reserved area of the thread object just contains the privilege stack:
203 *
204 * +------------+ <- thread.stack_obj = thread.arch.priv_stack_start
205 * | Priv Stack | } CONFIG_PRIVILEGED_STACK_SIZE
206 * +------------+ <- thread.stack_info.start
207 * | Thread |
208 * | stack |
209 * | |
210 * +............|
211 * | TLS | } thread.stack_info.delta
212 * +------------+ <- thread.stack_info.start + thread.stack_info.size
213 */
214#define ARCH_THREAD_STACK_RESERVED CONFIG_PRIVILEGED_STACK_SIZE
215#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
216 (ROUND_UP((size), Z_ARC_MPU_ALIGN))
217#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
218
219BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
220 "improper privilege stack size");
221#endif /* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT */
222#endif /* CONFIG_MPU_STACK_GUARD */
223
224#else /* !CONFIG_USERSPACE */
225
226#ifdef CONFIG_MPU_STACK_GUARD
227/* Only supported on ARC MPU V3 and higher. Reserve some memory for the stack
228 * guard. This is just a minimally-sized region at the beginning of the stack
229 * object, which is programmed to produce an exception if written to.
230 *
231 * +------------+ <- thread.stack_obj
232 * | Guard | } Z_ARC_STACK_GUARD_SIZE
233 * +------------+ <- thread.stack_info.start
234 * | Thread |
235 * | stack |
236 * | |
237 * +............|
238 * | TLS | } thread.stack_info.delta
239 * +------------+ <- thread.stack_info.start + thread.stack_info.size
240 */
241#define ARCH_THREAD_STACK_RESERVED Z_ARC_STACK_GUARD_SIZE
242#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
243/* Default for ARCH_THREAD_STACK_SIZE_ADJUST */
244#else /* !CONFIG_MPU_STACK_GUARD */
245/* No stack guard, no userspace, Use defaults for everything. */
246#endif /* CONFIG_MPU_STACK_GUARD */
247#endif /* CONFIG_USERSPACE */
248
249#ifdef CONFIG_ARC_MPU
250
251/* Legacy case: retain containing extern "C" with C++ */
253
254#define K_MEM_PARTITION_P_NA_U_NA AUX_MPU_ATTR_N
255#define K_MEM_PARTITION_P_RW_U_RW (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \
256 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
257#define K_MEM_PARTITION_P_RW_U_RO (AUX_MPU_ATTR_UR | \
258 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
259#define K_MEM_PARTITION_P_RW_U_NA (AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
260#define K_MEM_PARTITION_P_RO_U_RO (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)
261#define K_MEM_PARTITION_P_RO_U_NA (AUX_MPU_ATTR_KR)
262
263/* Execution-allowed attributes */
264#define K_MEM_PARTITION_P_RWX_U_RWX (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \
265 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \
266 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
267#define K_MEM_PARTITION_P_RWX_U_RX (AUX_MPU_ATTR_UR | \
268 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \
269 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
270#define K_MEM_PARTITION_P_RX_U_RX (AUX_MPU_ATTR_UR | \
271 AUX_MPU_ATTR_KR | \
272 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
273
274#define K_MEM_PARTITION_IS_WRITABLE(attr) \
275 ({ \
276 int __is_writable__; \
277 switch (attr & (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW)) { \
278 case (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW): \
279 case AUX_MPU_ATTR_UW: \
280 case AUX_MPU_ATTR_KW: \
281 __is_writable__ = 1; \
282 break; \
283 default: \
284 __is_writable__ = 0; \
285 break; \
286 } \
287 __is_writable__; \
288 })
289#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
290 ((attr) & (AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE))
291
292/*
293 * BUILD_ASSERT in case of MWDT is a bit more picky in performing compile-time check.
294 * For example it can't evaluate variable address at build time like GCC toolchain can do.
295 * That's why we provide custom _ARCH_MEM_PARTITION_ALIGN_CHECK implementation for MWDT toolchain
296 * with additional check for arguments availability in compile time.
297 */
298#ifdef __CCAC__
299#define IS_BUILTIN_MWDT(val) __builtin_constant_p((uintptr_t)(val))
300#if CONFIG_ARC_MPU_VER == 2 || CONFIG_ARC_MPU_VER == 3 || CONFIG_ARC_MPU_VER == 6
301#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
302 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? !((size) & ((size) - 1)) : 1, \
303 "partition size must be power of 2"); \
304 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) >= Z_ARC_MPU_ALIGN : 1, \
305 "partition size must be >= mpu address alignment."); \
306 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? IS_BUILTIN_MWDT(start) ? \
307 !((uintptr_t)(start) & ((size) - 1)) : 1 : 1, \
308 "partition start address must align with size.")
309#elif CONFIG_ARC_MPU_VER == 4
310#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
311 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) % Z_ARC_MPU_ALIGN == 0 : 1, \
312 "partition size must align with " STRINGIFY(Z_ARC_MPU_ALIGN)); \
313 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) >= Z_ARC_MPU_ALIGN : 1, \
314 "partition size must be >= " STRINGIFY(Z_ARC_MPU_ALIGN)); \
315 BUILD_ASSERT(IS_BUILTIN_MWDT(start) ? (uintptr_t)(start) % Z_ARC_MPU_ALIGN == 0 : 1, \
316 "partition start address must align with " STRINGIFY(Z_ARC_MPU_ALIGN))
317#endif
318#else /* __CCAC__ */
319#if CONFIG_ARC_MPU_VER == 2 || CONFIG_ARC_MPU_VER == 3 || CONFIG_ARC_MPU_VER == 6
320#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
321 BUILD_ASSERT(!((size) & ((size) - 1)), \
322 "partition size must be power of 2"); \
323 BUILD_ASSERT((size) >= Z_ARC_MPU_ALIGN, \
324 "partition size must be >= mpu address alignment."); \
325 BUILD_ASSERT(!((uintptr_t)(start) & ((size) - 1)), \
326 "partition start address must align with size.")
327#elif CONFIG_ARC_MPU_VER == 4
328#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
329 BUILD_ASSERT((size) % Z_ARC_MPU_ALIGN == 0, \
330 "partition size must align with " STRINGIFY(Z_ARC_MPU_ALIGN)); \
331 BUILD_ASSERT((size) >= Z_ARC_MPU_ALIGN, \
332 "partition size must be >= " STRINGIFY(Z_ARC_MPU_ALIGN)); \
333 BUILD_ASSERT((uintptr_t)(start) % Z_ARC_MPU_ALIGN == 0, \
334 "partition start address must align with " STRINGIFY(Z_ARC_MPU_ALIGN))
335#endif
336#endif /* __CCAC__ */
337#endif /* CONFIG_ARC_MPU*/
338
339/* Typedef for the k_mem_partition attribute*/
341
342static ALWAYS_INLINE void arch_nop(void)
343{
344 __builtin_arc_nop();
345}
346
347#endif /* _ASMLANGUAGE */
348
349#ifdef __cplusplus
350}
351#endif
352#endif /* ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_ */
static ALWAYS_INLINE void arch_nop(void)
Definition: arch.h:342
uint32_t k_mem_partition_attr_t
Definition: arch.h:220
#define ARCH_STACK_PTR_ALIGN
Definition: arch.h:93
ARCv2 public error handling.
ARCv2 public exception handling.
ARCv2 public kernel miscellaneous.
ARCv2 ARC Connect driver.
Per-arch thread definition.
ARCv2 public interrupt handling.
ARCv2 auxiliary registers definitions.
#define ALWAYS_INLINE
Definition: common.h:124
Devicetree main header.
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
Software-managed ISR table.