Zephyr Project API  3.2.0
A Scalable Open Source RTOS
arch.h
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1/*
2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
16#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ARCH_H_
17#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ARCH_H_
18
19/* Add include for DTS generated information */
20#include <zephyr/devicetree.h>
21
22/* ARM GPRs are often designated by two different names */
23#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
24
35
36#ifdef CONFIG_CPU_CORTEX_M
40#elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
43#if defined(CONFIG_AARCH32_ARMV8_R)
46#else
48#endif
49#endif
50
51#ifdef __cplusplus
52extern "C" {
53#endif
54
62#ifdef CONFIG_STACK_ALIGN_DOUBLE_WORD
63#define ARCH_STACK_PTR_ALIGN 8
64#else
65#define ARCH_STACK_PTR_ALIGN 4
66#endif
67
77#if defined(CONFIG_USERSPACE)
78#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
79#elif defined(CONFIG_ARM_AARCH32_MMU)
80#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MMU_REGION_MIN_ALIGN_AND_SIZE
81#else
82#define Z_THREAD_MIN_STACK_ALIGN ARCH_STACK_PTR_ALIGN
83#endif
84
132#if defined(CONFIG_MPU_STACK_GUARD)
133/* make sure there's more than enough space for an exception frame */
134#if CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE <= 0x20
135#define MPU_GUARD_ALIGN_AND_SIZE 0x40
136#else
137#define MPU_GUARD_ALIGN_AND_SIZE CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
138#endif
139#else
140#define MPU_GUARD_ALIGN_AND_SIZE 0
141#endif
142
153#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) \
154 && defined(CONFIG_MPU_STACK_GUARD)
155#if CONFIG_MPU_STACK_GUARD_MIN_SIZE_FLOAT <= 0x20
156#define MPU_GUARD_ALIGN_AND_SIZE_FLOAT 0x40
157#else
158#define MPU_GUARD_ALIGN_AND_SIZE_FLOAT CONFIG_MPU_STACK_GUARD_MIN_SIZE_FLOAT
159#endif
160#else
161#define MPU_GUARD_ALIGN_AND_SIZE_FLOAT 0
162#endif
163
171#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
172#define Z_MPU_GUARD_ALIGN (MAX(MPU_GUARD_ALIGN_AND_SIZE, \
173 MPU_GUARD_ALIGN_AND_SIZE_FLOAT))
174#else
175#define Z_MPU_GUARD_ALIGN MPU_GUARD_ALIGN_AND_SIZE
176#endif
177
178#if defined(CONFIG_USERSPACE) && \
179 defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
180/* This MPU requires regions to be sized to a power of two, and aligned to
181 * their own size. Since an MPU region must be able to cover the entire
182 * user-accessible stack buffer, we size/align to match. The privilege
183 * mode stack is generated elsewhere in memory.
184 */
185#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_POW2_CEIL(size)
186#define ARCH_THREAD_STACK_SIZE_ADJUST(size) Z_POW2_CEIL(size)
187#else
188#define ARCH_THREAD_STACK_OBJ_ALIGN(size) MAX(Z_THREAD_MIN_STACK_ALIGN, \
189 Z_MPU_GUARD_ALIGN)
190#ifdef CONFIG_USERSPACE
191#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
192 ROUND_UP(size, CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
193#endif
194#endif
195
196#ifdef CONFIG_MPU_STACK_GUARD
197/* Kernel-only stacks need an MPU guard region programmed at the beginning of
198 * the stack object, so align the object appropriately.
199 */
200#define ARCH_KERNEL_STACK_RESERVED MPU_GUARD_ALIGN_AND_SIZE
201#define ARCH_KERNEL_STACK_OBJ_ALIGN Z_MPU_GUARD_ALIGN
202#endif
203
204/* On arm, all MPU guards are carve-outs. */
205#define ARCH_THREAD_STACK_RESERVED 0
206
207/* Legacy case: retain containing extern "C" with C++ */
208#ifdef CONFIG_ARM_MPU
209#ifdef CONFIG_CPU_HAS_ARM_MPU
211#endif /* CONFIG_CPU_HAS_ARM_MPU */
212#ifdef CONFIG_CPU_HAS_NXP_MPU
214#endif /* CONFIG_CPU_HAS_NXP_MPU */
215#endif /* CONFIG_ARM_MPU */
216#ifdef CONFIG_ARM_AARCH32_MMU
218#endif /* CONFIG_ARM_AARCH32_MMU */
219
220#ifdef __cplusplus
221}
222#endif
223
224#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ARCH_H_ */
ARM AArch32 public interrupt handling.
Per-arch thread definition.
ARM AArch32 public error handling.
ARM AArch32 public exception handling.
ARM AArch32 public kernel miscellaneous.
Devicetree main header.
ARM CORTEX-M memory map.
ARM AArch32 NMI routines.