pinctrl_soc_gd32_common.h

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/*
 * Copyright (c) 2021 Teslabs Engineering S.L.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
 
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
 
#ifdef CONFIG_PINCTRL_GD32_AF
#include <dt-bindings/pinctrl/gd32-af.h>
#else
#include <dt-bindings/pinctrl/gd32-afio.h>
#endif /* CONFIG_PINCTRL_GD32_AF */
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef uint32_t pinctrl_soc_pin_t;
 
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)                           \
        (DT_PROP_BY_IDX(node_id, prop, idx) |                                  \
         ((GD32_PUPD_PULLUP * DT_PROP(node_id, bias_pull_up))                  \
          << GD32_PUPD_POS) |                                                  \
         ((GD32_PUPD_PULLDOWN * DT_PROP(node_id, bias_pull_down))              \
          << GD32_PUPD_POS) |                                                  \
         ((GD32_OTYPE_OD * DT_PROP(node_id, drive_open_drain))                 \
          << GD32_OTYPE_POS) |                                                 \
         (DT_ENUM_IDX(node_id, slew_rate) << GD32_OSPEED_POS)),
 
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                               \
        {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),                     \
                                DT_FOREACH_PROP_ELEM, pinmux,                  \
                                Z_PINCTRL_STATE_PIN_INIT)}
 
#define GD32_PUPD_NONE 0U
#define GD32_PUPD_PULLUP 1U
#define GD32_PUPD_PULLDOWN 2U
 
#define GD32_OTYPE_PP 0U
#define GD32_OTYPE_OD 1U
 
#ifdef CONFIG_PINCTRL_GD32_AF
#define GD32_OSPEED_2MHZ 0U
#ifdef CONFIG_SOC_SERIES_GD32F3X0
#define GD32_OSPEED_10MHZ 1U
#define GD32_OSPEED_50MHZ 3U
#else
#define GD32_OSPEED_25MHZ 1U
#define GD32_OSPEED_50MHZ 2U
#define GD32_OSPEED_MAX 3U
#endif /* CONFIG_SOC_SERIES_GD32F3X0 */
#else
#define GD32_OSPEED_10MHZ 0U
#define GD32_OSPEED_2MHZ 1U
#define GD32_OSPEED_50MHZ 2U
#define GD32_OSPEED_MAX 3U
#endif /* CONFIG_PINCTRL_GD32_AF */
 
#define GD32_PUPD_MSK 0x3U
#define GD32_PUPD_POS 29U
#define GD32_OTYPE_MSK 0x1U
#define GD32_OTYPE_POS 28U
#define GD32_OSPEED_MSK 0x3U
#define GD32_OSPEED_POS 26U
 
#define GD32_PUPD_GET(pincfg) \
        (((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
 
#define GD32_OTYPE_GET(pincfg) \
        (((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
 
#define GD32_OSPEED_GET(pincfg) \
        (((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
 
#ifdef __cplusplus
}
#endif
 
#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_ */