Zephyr Project API  3.2.0
A Scalable Open Source RTOS
exp.h
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1/*
2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
3 * Copyright (c) 2018 Foundries.io Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
15#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_
16#define ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_
17
18#ifndef _ASMLANGUAGE
19#include <zephyr/types.h>
20#include <zephyr/toolchain.h>
21
22#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
23#include <soc_context.h>
24#endif
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30/*
31 * The name of the structure which contains soc-specific state, if
32 * any, as well as the soc_esf_t typedef below, are part of the RISC-V
33 * arch API.
34 *
35 * The contents of the struct are provided by a SOC-specific
36 * definition in soc_context.h.
37 */
38#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
39struct soc_esf {
40 SOC_ESF_MEMBERS;
41};
42#endif
43
44#if !defined(RV_FP_TYPE) && defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
45#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
46#define RV_FP_TYPE uint64_t
47#else
48#define RV_FP_TYPE uint32_t
49#endif
50#endif
51
52struct __esf {
53 unsigned long ra; /* return address */
54
55 unsigned long t0; /* Caller-saved temporary register */
56 unsigned long t1; /* Caller-saved temporary register */
57 unsigned long t2; /* Caller-saved temporary register */
58#if !defined(CONFIG_RISCV_ISA_RV32E)
59 unsigned long t3; /* Caller-saved temporary register */
60 unsigned long t4; /* Caller-saved temporary register */
61 unsigned long t5; /* Caller-saved temporary register */
62 unsigned long t6; /* Caller-saved temporary register */
63#endif /* !CONFIG_RISCV_ISA_RV32E */
64
65 unsigned long a0; /* function argument/return value */
66 unsigned long a1; /* function argument */
67 unsigned long a2; /* function argument */
68 unsigned long a3; /* function argument */
69 unsigned long a4; /* function argument */
70 unsigned long a5; /* function argument */
71#if !defined(CONFIG_RISCV_ISA_RV32E)
72 unsigned long a6; /* function argument */
73 unsigned long a7; /* function argument */
74#endif /* !CONFIG_RISCV_ISA_RV32E */
75
76 unsigned long mepc; /* machine exception program counter */
77 unsigned long mstatus; /* machine status register */
78
79 unsigned long s0; /* callee-saved s0 */
80
81#ifdef CONFIG_USERSPACE
82 unsigned long sp; /* preserved (user or kernel) stack pointer */
83#endif
84
85#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
86 RV_FP_TYPE ft0; /* Caller-saved temporary floating register */
87 RV_FP_TYPE ft1; /* Caller-saved temporary floating register */
88 RV_FP_TYPE ft2; /* Caller-saved temporary floating register */
89 RV_FP_TYPE ft3; /* Caller-saved temporary floating register */
90 RV_FP_TYPE ft4; /* Caller-saved temporary floating register */
91 RV_FP_TYPE ft5; /* Caller-saved temporary floating register */
92 RV_FP_TYPE ft6; /* Caller-saved temporary floating register */
93 RV_FP_TYPE ft7; /* Caller-saved temporary floating register */
94 RV_FP_TYPE ft8; /* Caller-saved temporary floating register */
95 RV_FP_TYPE ft9; /* Caller-saved temporary floating register */
96 RV_FP_TYPE ft10; /* Caller-saved temporary floating register */
97 RV_FP_TYPE ft11; /* Caller-saved temporary floating register */
98 RV_FP_TYPE fa0; /* function argument/return value */
99 RV_FP_TYPE fa1; /* function argument/return value */
100 RV_FP_TYPE fa2; /* function argument */
101 RV_FP_TYPE fa3; /* function argument */
102 RV_FP_TYPE fa4; /* function argument */
103 RV_FP_TYPE fa5; /* function argument */
104 RV_FP_TYPE fa6; /* function argument */
105 RV_FP_TYPE fa7; /* function argument */
106#endif
107
108#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
109 struct soc_esf soc_context;
110#endif
111} __aligned(16);
112
113typedef struct __esf z_arch_esf_t;
114#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
115typedef struct soc_esf soc_esf_t;
116#endif
117
118#ifdef __cplusplus
119}
120#endif
121
122#endif /* _ASMLANGUAGE */
123
124#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_ */
#define RV_FP_TYPE
Definition: exp.h:48
struct k_thread t2
Definition: main.c:26
Macros to abstract toolchain specific capabilities.