Zephyr Project API  3.2.0
A Scalable Open Source RTOS
stm32f3_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
8
10#define STM32_CLOCK_BUS_AHB1 0x014
11#define STM32_CLOCK_BUS_APB2 0x018
12#define STM32_CLOCK_BUS_APB1 0x01c
13
14#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
15#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
16
18/* RM0316, ยง9.4.13 Clock configuration register (RCC_CFGR3) */
19
21#define STM32_SRC_HSI 0x001
22#define STM32_SRC_LSE 0x002
23/* #define STM32_SRC_HSI48 0x003 */
25#define STM32_SRC_SYSCLK 0x004
27#define STM32_SRC_PCLK 0x005
29#define STM32_SRC_PLLCLK 0x006
30
45#define STM32_CLOCK_REG_MASK 0xFFU
46#define STM32_CLOCK_REG_SHIFT 0U
47#define STM32_CLOCK_SHIFT_MASK 0x1FU
48#define STM32_CLOCK_SHIFT_SHIFT 8U
49#define STM32_CLOCK_MASK_MASK 0x7U
50#define STM32_CLOCK_MASK_SHIFT 13U
51#define STM32_CLOCK_VAL_MASK 0x7U
52#define STM32_CLOCK_VAL_SHIFT 16U
53
54#define STM32_CLOCK(val, mask, shift, reg) \
55 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
56 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
57 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
58 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
59
61#define CFGR3_REG 0x30
62
65#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
66#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
67#define I2C2_SEL(val) STM32_CLOCK(val, 1, 5, CFGR3_REG)
68#define I2C3_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG)
69#define TIM1_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG)
70#define TIM8_SEL(val) STM32_CLOCK(val, 1, 9, CFGR3_REG)
71#define TIM15_SEL(val) STM32_CLOCK(val, 1, 10, CFGR3_REG)
72#define TIM16_SEL(val) STM32_CLOCK(val, 1, 11, CFGR3_REG)
73#define TIM17_SEL(val) STM32_CLOCK(val, 1, 13, CFGR3_REG)
74#define TIM20_SEL(val) STM32_CLOCK(val, 1, 15, CFGR3_REG)
75#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG)
76#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG)
77#define USART4_SEL(val) STM32_CLOCK(val, 3, 20, CFGR3_REG)
78#define USART5_SEL(val) STM32_CLOCK(val, 3, 22, CFGR3_REG)
79#define TIM2_SEL(val) STM32_CLOCK(val, 1, 24, CFGR3_REG)
80#define TIM3_4_SEL(val) STM32_CLOCK(val, 1, 25, CFGR3_REG)
81
82#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */