Zephyr Project API  3.2.0
A Scalable Open Source RTOS
stm32g0_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
8
10#define STM32_CLOCK_BUS_IOP 0x034
11#define STM32_CLOCK_BUS_AHB1 0x038
12#define STM32_CLOCK_BUS_APB1 0x03c
13#define STM32_CLOCK_BUS_APB2 0x040
14
15#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
16#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
17
19/* RM0444, ยง5.4.21/22 Clock configuration register (RCC_CCIPRx) */
20
22#define STM32_SRC_HSI 0x001
23#define STM32_SRC_MSI 0x002
24#define STM32_SRC_HSE 0x003
25#define STM32_SRC_LSE 0x004
26#define STM32_SRC_LSI 0x005
28#define STM32_SRC_SYSCLK 0x006
30#define STM32_SRC_PCLK 0x007
32#define STM32_SRC_PLL_P 0x008
33#define STM32_SRC_PLL_Q 0x009
34#define STM32_SRC_PLL_R 0x00a
35
50#define STM32_CLOCK_REG_MASK 0xFFU
51#define STM32_CLOCK_REG_SHIFT 0U
52#define STM32_CLOCK_SHIFT_MASK 0x1FU
53#define STM32_CLOCK_SHIFT_SHIFT 8U
54#define STM32_CLOCK_MASK_MASK 0x7U
55#define STM32_CLOCK_MASK_SHIFT 13U
56#define STM32_CLOCK_VAL_MASK 0x7U
57#define STM32_CLOCK_VAL_SHIFT 16U
58
59#define STM32_CLOCK(val, mask, shift, reg) \
60 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
61 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
62 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
63 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
64
66#define CCIPR_REG 0x54
67#define CCIPR2_REG 0x58
68
71#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
72#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
73#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
74#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR_REG)
75#define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
76#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
77#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
78#define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
79#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
80#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
81#define TIM1_SEL(val) STM32_CLOCK(val, 1, 22, CCIPR_REG)
82#define TIM15_SEL(val) STM32_CLOCK(val, 1, 24, CCIPR_REG)
83#define RNG_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
84#define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
86#define I2S1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG)
87#define I2S2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR2_REG)
88#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR2_REG)
89#define USB_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG)
90
91
92
93
94#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */