Zephyr Project API
3.2.0
A Scalable Open Source RTOS
stm32h7_clock.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2022 Linaro Limited
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
7
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
8
11
/* RM0468, Table 56 Kernel clock dictribution summary */
12
14
#define STM32_SRC_PLL1_P 0x001
15
#define STM32_SRC_PLL1_Q 0x002
16
#define STM32_SRC_PLL1_R 0x003
18
/* #define STM32_SRC_PLL2_P 0x004 */
19
/* #define STM32_SRC_PLL2_Q 0x005 */
20
/* #define STM32_SRC_PLL2_R 0x006 */
21
#define STM32_SRC_PLL3_P 0x007
22
#define STM32_SRC_PLL3_Q 0x008
23
#define STM32_SRC_PLL3_R 0x009
25
#define STM32_SRC_HSE 0x00A
26
#define STM32_SRC_LSE 0x00B
27
#define STM32_SRC_LSI 0x00C
29
/* #define STM32_SRC_HSI48 0x00D */
30
#define STM32_SRC_HSI_KER 0x00E
/* HSI + HSIKERON */
31
#define STM32_SRC_CSI_KER 0x00F
/* CSI + CSIKERON */
33
#define STM32_SRC_SYSCLK 0x010
35
/* #define STM32_SRC_I2SCKIN 0x011 */
36
/* #define STM32_SRC_SPDIFRX 0x012 */
38
#define STM32_SRC_CKPER 0x013
39
41
#define STM32_CLOCK_BUS_AHB3 0x0D4
42
#define STM32_CLOCK_BUS_AHB1 0x0D8
43
#define STM32_CLOCK_BUS_AHB2 0x0DC
44
#define STM32_CLOCK_BUS_AHB4 0x0E0
45
#define STM32_CLOCK_BUS_APB3 0x0E4
46
#define STM32_CLOCK_BUS_APB1 0x0E8
47
#define STM32_CLOCK_BUS_APB1_2 0x0EC
48
#define STM32_CLOCK_BUS_APB2 0x0F0
49
#define STM32_CLOCK_BUS_APB4 0x0F4
/* TBD: To remove ? */
51
#define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1
52
#define STM32_SRC_PCLK2 STM32_CLOCK_BUS_APB2
53
#define STM32_SRC_HCLK3 STM32_CLOCK_BUS_AHB3
54
#define STM32_SRC_PCLK3 STM32_CLOCK_BUS_APB3
55
#define STM32_SRC_PCLK4 STM32_CLOCK_BUS_APB4
56
57
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
58
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
59
74
#define STM32_CLOCK_REG_MASK 0xFFU
75
#define STM32_CLOCK_REG_SHIFT 0U
76
#define STM32_CLOCK_SHIFT_MASK 0x1FU
77
#define STM32_CLOCK_SHIFT_SHIFT 8U
78
#define STM32_CLOCK_MASK_MASK 0x7U
79
#define STM32_CLOCK_MASK_SHIFT 13U
80
#define STM32_CLOCK_VAL_MASK 0x7U
81
#define STM32_CLOCK_VAL_SHIFT 16U
82
83
#define STM32_CLOCK(val, mask, shift, reg) \
84
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
85
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
86
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
87
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
88
90
#define D1CCIPR_REG 0x4C
91
#define D2CCIP1R_REG 0x50
92
#define D2CCIP2R_REG 0x54
93
#define D3CCIPR_REG 0x58
94
97
#define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG)
98
#define QSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG)
99
#define DSI_SEL(val) STM32_CLOCK(val, 1, 8, D1CCIPR_REG)
100
#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 16, D1CCIPR_REG)
101
#define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG)
102
/* Device domain clocks selection helpers (RM0468.pdf) */
103
#define OSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG)
105
#define SAI1_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP1R_REG)
106
#define SAI23_SEL(val) STM32_CLOCK(val, 7, 6, D2CCIP1R_REG)
107
#define SPI123_SEL(val) STM32_CLOCK(val, 7, 12, D2CCIP1R_REG)
108
#define SPI45_SEL(val) STM32_CLOCK(val, 7, 16, D2CCIP1R_REG)
109
#define SPDIF_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP1R_REG)
110
#define DFSDM1_SEL(val) STM32_CLOCK(val, 1, 24, D2CCIP1R_REG)
111
#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 28, D2CCIP1R_REG)
112
#define SWP_SEL(val) STM32_CLOCK(val, 1, 31, D2CCIP1R_REG)
114
#define USART2345678_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP2R_REG)
115
#define USART16_SEL(val) STM32_CLOCK(val, 7, 3, D2CCIP2R_REG)
116
#define RNG_SEL(val) STM32_CLOCK(val, 3, 8, D2CCIP2R_REG)
117
#define I2C123_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIP2R_REG)
118
#define USB_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP2R_REG)
119
#define CEC_SEL(val) STM32_CLOCK(val, 3, 22, D2CCIP2R_REG)
120
#define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 28, D2CCIP2R_REG)
122
#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, D3CCIPR_REG)
123
#define I2C4_SEL(val) STM32_CLOCK(val, 3, 8, D3CCIPR_REG)
124
#define LPTIM2_SEL(val) STM32_CLOCK(val, 7, 10, D3CCIPR_REG)
125
#define LPTIM345_SEL(val) STM32_CLOCK(val, 7, 13, D3CCIPR_REG)
126
#define ADC_SEL(val) STM32_CLOCK(val, 3, 16, D3CCIPR_REG)
127
#define SAI4A_SEL(val) STM32_CLOCK(val, 7, 21, D3CCIPR_REG)
128
#define SAI4B_SEL(val) STM32_CLOCK(val, 7, 24, D3CCIPR_REG)
129
#define SPI6_SEL(val) STM32_CLOCK(val, 7, 28, D3CCIPR_REG)
130
131
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */
include
zephyr
dt-bindings
clock
stm32h7_clock.h
Generated on Tue Feb 28 2023 15:43:19 for Zephyr Project API by
1.9.2
1.9.2