Zephyr Project API  3.2.0
A Scalable Open Source RTOS
stm32u5_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
8
11/* RM0468, Table 56 Kernel clock distribution summary */
12
14#define STM32_SRC_PLL1_P 0x001
15#define STM32_SRC_PLL1_Q 0x002
16#define STM32_SRC_PLL1_R 0x003
17#define STM32_SRC_PLL2_P 0x004
18#define STM32_SRC_PLL2_Q 0x005
19#define STM32_SRC_PLL2_R 0x006
20#define STM32_SRC_PLL3_P 0x007
21#define STM32_SRC_PLL3_Q 0x008
22#define STM32_SRC_PLL3_R 0x009
24#define STM32_SRC_HSE 0x00A
25#define STM32_SRC_LSE 0x00B
26#define STM32_SRC_LSI 0x00C
27#define STM32_SRC_HSI16 0x00D
28/* #define STM32_SRC_HSI48 0x00E */
29#define STM32_SRC_MSIS 0x00F
30#define STM32_SRC_MSIK 0x010
32#define STM32_SRC_SYSCLK 0x011
34/* #define STM32_SRC_ICLK 0x012 */
35
37#define STM32_CLOCK_BUS_AHB1 0x088
38#define STM32_CLOCK_BUS_AHB2 0x08C
39#define STM32_CLOCK_BUS_AHB2_2 0x090
40#define STM32_CLOCK_BUS_AHB3 0x094
41#define STM32_CLOCK_BUS_APB1 0x09C
42#define STM32_CLOCK_BUS_APB1_2 0x0A0
43#define STM32_CLOCK_BUS_APB2 0x0A4
44#define STM32_CLOCK_BUS_APB3 0x0A8
45
46#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
47#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
48
63#define STM32_CLOCK_REG_MASK 0xFFU
64#define STM32_CLOCK_REG_SHIFT 0U
65#define STM32_CLOCK_SHIFT_MASK 0x1FU
66#define STM32_CLOCK_SHIFT_SHIFT 8U
67#define STM32_CLOCK_MASK_MASK 0x7U
68#define STM32_CLOCK_MASK_SHIFT 13U
69#define STM32_CLOCK_VAL_MASK 0x7U
70#define STM32_CLOCK_VAL_SHIFT 16U
71
72#define STM32_CLOCK(val, mask, shift, reg) \
73 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
74 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
75 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
76 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
77
79#define CCIPR1_REG 0xE0
80#define CCIPR2_REG 0xE4
81#define CCIPR3_REG 0xE8
82
85#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG)
86#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG)
87#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR1_REG)
88#define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR1_REG)
89#define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR1_REG)
90#define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG)
91#define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR1_REG)
92#define I2C4_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR1_REG)
93#define SPI2_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR1_REG)
94#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR1_REG)
95#define SPI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR1_REG)
96#define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR1_REG)
97#define FDCAN1_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR1_REG)
98#define ICKLK_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR1_REG)
99#define TIMIC_SEL(val) STM32_CLOCK(val, 7, 29, CCIPR1_REG)
101#define MDF1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR2_REG)
102#define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG)
103#define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG)
104#define SAE_SEL(val) STM32_CLOCK(val, 1, 11, CCIPR2_REG)
105#define RNG_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG)
106#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG)
107#define OCTOSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG)
109#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG)
110#define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG)
111#define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG)
112#define LPTIM34_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR3_REG)
113#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR3_REG)
114#define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG)
115#define DAC1_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR3_REG)
116#define ADF1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR3_REG)
117
118#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */