Zephyr Project API  3.3.0
A Scalable Open Source RTOS
arch.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2014 Wind River Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
16#ifndef ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_
17#define ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_
18
19#include <zephyr/devicetree.h>
20#include <zephyr/sw_isr_table.h>
24#include "sys-io-common.h"
25
34
35#ifdef CONFIG_ARC_CONNECT
37#endif
38
39#ifdef CONFIG_ISA_ARCV2
40#include "v2/sys_io.h"
41#ifdef CONFIG_ARC_HAS_SECURE
43#endif
44#endif
45
46#if defined(CONFIG_ARC_FIRQ) && defined(CONFIG_ISA_ARCV3)
47#error "Unsupported configuration: ARC_FIRQ and ISA_ARCV3"
48#endif
49
50/*
51 * We don't allow the configuration with FIRQ enabled and only one interrupt priority level
52 * (so all interrupts are FIRQ). Such configuration isn't supported in software and it is not
53 * beneficial from the performance point of view.
54 */
55#if defined(CONFIG_ARC_FIRQ) && CONFIG_NUM_IRQ_PRIO_LEVELS < 2
56#error "Unsupported configuration: ARC_FIRQ and (NUM_IRQ_PRIO_LEVELS < 2)"
57#endif
58
59#if CONFIG_RGF_NUM_BANKS > 1 && !defined(CONFIG_ARC_FIRQ)
60#error "Unsupported configuration: (RGF_NUM_BANKS > 1) and !ARC_FIRQ"
61#endif
62
63/*
64 * It's required to have more than one interrupt priority level to use second register bank
65 * - otherwise all interrupts will use same register bank. Such configuration isn't supported in
66 * software and it is not beneficial from the performance point of view.
67 */
68#if CONFIG_RGF_NUM_BANKS > 1 && CONFIG_NUM_IRQ_PRIO_LEVELS < 2
69#error "Unsupported configuration: (RGF_NUM_BANKS > 1) and (NUM_IRQ_PRIO_LEVELS < 2)"
70#endif
71
72#if defined(CONFIG_ARC_FIRQ_STACK) && !defined(CONFIG_ARC_FIRQ)
73#error "Unsupported configuration: ARC_FIRQ_STACK and !ARC_FIRQ"
74#endif
75
76#if defined(CONFIG_ARC_FIRQ_STACK) && CONFIG_RGF_NUM_BANKS < 2
77#error "Unsupported configuration: ARC_FIRQ_STACK and (RGF_NUM_BANKS < 2)"
78#endif
79
80/* In case of ARC 2+2 secure mode enabled the firq are not supported by HW */
81#if defined(CONFIG_ARC_FIRQ) && defined(CONFIG_ARC_HAS_SECURE)
82#error "Unsupported configuration: ARC_FIRQ and ARC_HAS_SECURE"
83#endif
84
85#if defined(CONFIG_SMP) && !defined(CONFIG_MULTITHREADING)
86#error "Non-multithreading mode isn't supported on SMP targets"
87#endif
88
89#ifndef _ASMLANGUAGE
90
91#ifdef __cplusplus
92extern "C" {
93#endif
94
95#ifdef CONFIG_64BIT
96#define ARCH_STACK_PTR_ALIGN 8
97#else
98#define ARCH_STACK_PTR_ALIGN 4
99#endif /* CONFIG_64BIT */
100
101BUILD_ASSERT(CONFIG_ISR_STACK_SIZE % ARCH_STACK_PTR_ALIGN == 0,
102 "CONFIG_ISR_STACK_SIZE must be a multiple of ARCH_STACK_PTR_ALIGN");
103
104BUILD_ASSERT(CONFIG_ARC_EXCEPTION_STACK_SIZE % ARCH_STACK_PTR_ALIGN == 0,
105 "CONFIG_ARC_EXCEPTION_STACK_SIZE must be a multiple of ARCH_STACK_PTR_ALIGN");
106
107/* Indicate, for a minimally sized MPU region, how large it must be and what
108 * its base address must be aligned to.
109 *
110 * For regions that are NOT the minimum size, this define has no semantics
111 * on ARC MPUv2 as its regions must be power of two size and aligned to their
112 * own size. On ARC MPUv4, region sizes are arbitrary and this just indicates
113 * the required size granularity.
114 */
115#ifdef CONFIG_ARC_CORE_MPU
116#if CONFIG_ARC_MPU_VER == 2
117#define Z_ARC_MPU_ALIGN 2048
118#elif (CONFIG_ARC_MPU_VER == 3) || (CONFIG_ARC_MPU_VER == 4) || (CONFIG_ARC_MPU_VER == 6)
119#define Z_ARC_MPU_ALIGN 32
120#else
121#error "Unsupported MPU version"
122#endif
123#endif
124
125#ifdef CONFIG_MPU_STACK_GUARD
126#define Z_ARC_STACK_GUARD_SIZE Z_ARC_MPU_ALIGN
127#else
128#define Z_ARC_STACK_GUARD_SIZE 0
129#endif
130
131/* Kernel-only stacks have the following layout if a stack guard is enabled:
132 *
133 * +------------+ <- thread.stack_obj
134 * | Guard | } Z_ARC_STACK_GUARD_SIZE
135 * +------------+ <- thread.stack_info.start
136 * | Kernel |
137 * | stack |
138 * | |
139 * +............|
140 * | TLS | } thread.stack_info.delta
141 * +------------+ <- thread.stack_info.start + thread.stack_info.size
142 */
143#ifdef CONFIG_MPU_STACK_GUARD
144#define ARCH_KERNEL_STACK_RESERVED Z_ARC_STACK_GUARD_SIZE
145#define ARCH_KERNEL_STACK_OBJ_ALIGN Z_ARC_MPU_ALIGN
146#endif
147
148#ifdef CONFIG_USERSPACE
149/* Any thread running In user mode will have full access to the region denoted
150 * by thread.stack_info.
151 *
152 * Thread-local storage is at the very highest memory locations of this area.
153 * Memory for TLS and any initial random stack pointer offset is captured
154 * in thread.stack_info.delta.
155 */
156#ifdef CONFIG_MPU_STACK_GUARD
157/* MPU guards are only supported with V3 MPU and later. In this configuration
158 * the stack object will contain the MPU guard, the privilege stack, and then
159 * the stack buffer in that order:
160 *
161 * +------------+ <- thread.stack_obj
162 * | Guard | } Z_ARC_STACK_GUARD_SIZE
163 * +------------+ <- thread.arch.priv_stack_start
164 * | Priv Stack | } CONFIG_PRIVILEGED_STACK_SIZE
165 * +------------+ <- thread.stack_info.start
166 * | Thread |
167 * | stack |
168 * | |
169 * +............|
170 * | TLS | } thread.stack_info.delta
171 * +------------+ <- thread.stack_info.start + thread.stack_info.size
172 */
173#define ARCH_THREAD_STACK_RESERVED (Z_ARC_STACK_GUARD_SIZE + \
174 CONFIG_PRIVILEGED_STACK_SIZE)
175#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
176/* We need to be able to exactly cover the stack buffer with an MPU region,
177 * so round its size up to the required granularity of the MPU
178 */
179#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
180 (ROUND_UP((size), Z_ARC_MPU_ALIGN))
181BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
182 "improper privilege stack size");
183#else /* !CONFIG_MPU_STACK_GUARD */
184/* Userspace enabled, but supervisor stack guards are not in use */
185#ifdef CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
186/* Use defaults for everything. The privilege elevation stack is located
187 * in another area of memory generated at build time by gen_kobject_list.py
188 *
189 * +------------+ <- thread.arch.priv_stack_start
190 * | Priv Stack | } Z_KERNEL_STACK_LEN(CONFIG_PRIVILEGED_STACK_SIZE)
191 * +------------+
192 *
193 * +------------+ <- thread.stack_obj = thread.stack_info.start
194 * | Thread |
195 * | stack |
196 * | |
197 * +............|
198 * | TLS | } thread.stack_info.delta
199 * +------------+ <- thread.stack_info.start + thread.stack_info.size
200 */
201#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
202 Z_POW2_CEIL(ROUND_UP((size), Z_ARC_MPU_ALIGN))
203#define ARCH_THREAD_STACK_OBJ_ALIGN(size) \
204 ARCH_THREAD_STACK_SIZE_ADJUST(size)
205#define ARCH_THREAD_STACK_RESERVED 0
206#else /* !CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT */
207/* Reserved area of the thread object just contains the privilege stack:
208 *
209 * +------------+ <- thread.stack_obj = thread.arch.priv_stack_start
210 * | Priv Stack | } CONFIG_PRIVILEGED_STACK_SIZE
211 * +------------+ <- thread.stack_info.start
212 * | Thread |
213 * | stack |
214 * | |
215 * +............|
216 * | TLS | } thread.stack_info.delta
217 * +------------+ <- thread.stack_info.start + thread.stack_info.size
218 */
219#define ARCH_THREAD_STACK_RESERVED CONFIG_PRIVILEGED_STACK_SIZE
220#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
221 (ROUND_UP((size), Z_ARC_MPU_ALIGN))
222#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
223
224BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
225 "improper privilege stack size");
226#endif /* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT */
227#endif /* CONFIG_MPU_STACK_GUARD */
228
229#else /* !CONFIG_USERSPACE */
230
231#ifdef CONFIG_MPU_STACK_GUARD
232/* Only supported on ARC MPU V3 and higher. Reserve some memory for the stack
233 * guard. This is just a minimally-sized region at the beginning of the stack
234 * object, which is programmed to produce an exception if written to.
235 *
236 * +------------+ <- thread.stack_obj
237 * | Guard | } Z_ARC_STACK_GUARD_SIZE
238 * +------------+ <- thread.stack_info.start
239 * | Thread |
240 * | stack |
241 * | |
242 * +............|
243 * | TLS | } thread.stack_info.delta
244 * +------------+ <- thread.stack_info.start + thread.stack_info.size
245 */
246#define ARCH_THREAD_STACK_RESERVED Z_ARC_STACK_GUARD_SIZE
247#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
248/* Default for ARCH_THREAD_STACK_SIZE_ADJUST */
249#else /* !CONFIG_MPU_STACK_GUARD */
250/* No stack guard, no userspace, Use defaults for everything. */
251#endif /* CONFIG_MPU_STACK_GUARD */
252#endif /* CONFIG_USERSPACE */
253
254#ifdef CONFIG_ARC_MPU
255
256/* Legacy case: retain containing extern "C" with C++ */
258
259#define K_MEM_PARTITION_P_NA_U_NA AUX_MPU_ATTR_N
260#define K_MEM_PARTITION_P_RW_U_RW (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \
261 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
262#define K_MEM_PARTITION_P_RW_U_RO (AUX_MPU_ATTR_UR | \
263 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
264#define K_MEM_PARTITION_P_RW_U_NA (AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
265#define K_MEM_PARTITION_P_RO_U_RO (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)
266#define K_MEM_PARTITION_P_RO_U_NA (AUX_MPU_ATTR_KR)
267
268/* Execution-allowed attributes */
269#define K_MEM_PARTITION_P_RWX_U_RWX (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \
270 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \
271 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
272#define K_MEM_PARTITION_P_RWX_U_RX (AUX_MPU_ATTR_UR | \
273 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \
274 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
275#define K_MEM_PARTITION_P_RX_U_RX (AUX_MPU_ATTR_UR | \
276 AUX_MPU_ATTR_KR | \
277 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
278
279#define K_MEM_PARTITION_IS_WRITABLE(attr) \
280 ({ \
281 int __is_writable__; \
282 switch (attr & (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW)) { \
283 case (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW): \
284 case AUX_MPU_ATTR_UW: \
285 case AUX_MPU_ATTR_KW: \
286 __is_writable__ = 1; \
287 break; \
288 default: \
289 __is_writable__ = 0; \
290 break; \
291 } \
292 __is_writable__; \
293 })
294#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
295 ((attr) & (AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE))
296
297/*
298 * BUILD_ASSERT in case of MWDT is a bit more picky in performing compile-time check.
299 * For example it can't evaluate variable address at build time like GCC toolchain can do.
300 * That's why we provide custom _ARCH_MEM_PARTITION_ALIGN_CHECK implementation for MWDT toolchain
301 * with additional check for arguments availability in compile time.
302 */
303#ifdef __CCAC__
304#define IS_BUILTIN_MWDT(val) __builtin_constant_p((uintptr_t)(val))
305#if CONFIG_ARC_MPU_VER == 2 || CONFIG_ARC_MPU_VER == 3 || CONFIG_ARC_MPU_VER == 6
306#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
307 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? !((size) & ((size) - 1)) : 1, \
308 "partition size must be power of 2"); \
309 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) >= Z_ARC_MPU_ALIGN : 1, \
310 "partition size must be >= mpu address alignment."); \
311 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? IS_BUILTIN_MWDT(start) ? \
312 !((uintptr_t)(start) & ((size) - 1)) : 1 : 1, \
313 "partition start address must align with size.")
314#elif CONFIG_ARC_MPU_VER == 4
315#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
316 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) % Z_ARC_MPU_ALIGN == 0 : 1, \
317 "partition size must align with " STRINGIFY(Z_ARC_MPU_ALIGN)); \
318 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) >= Z_ARC_MPU_ALIGN : 1, \
319 "partition size must be >= " STRINGIFY(Z_ARC_MPU_ALIGN)); \
320 BUILD_ASSERT(IS_BUILTIN_MWDT(start) ? (uintptr_t)(start) % Z_ARC_MPU_ALIGN == 0 : 1, \
321 "partition start address must align with " STRINGIFY(Z_ARC_MPU_ALIGN))
322#endif
323#else /* __CCAC__ */
324#if CONFIG_ARC_MPU_VER == 2 || CONFIG_ARC_MPU_VER == 3 || CONFIG_ARC_MPU_VER == 6
325#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
326 BUILD_ASSERT(!((size) & ((size) - 1)), \
327 "partition size must be power of 2"); \
328 BUILD_ASSERT((size) >= Z_ARC_MPU_ALIGN, \
329 "partition size must be >= mpu address alignment."); \
330 BUILD_ASSERT(!((uintptr_t)(start) & ((size) - 1)), \
331 "partition start address must align with size.")
332#elif CONFIG_ARC_MPU_VER == 4
333#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
334 BUILD_ASSERT((size) % Z_ARC_MPU_ALIGN == 0, \
335 "partition size must align with " STRINGIFY(Z_ARC_MPU_ALIGN)); \
336 BUILD_ASSERT((size) >= Z_ARC_MPU_ALIGN, \
337 "partition size must be >= " STRINGIFY(Z_ARC_MPU_ALIGN)); \
338 BUILD_ASSERT((uintptr_t)(start) % Z_ARC_MPU_ALIGN == 0, \
339 "partition start address must align with " STRINGIFY(Z_ARC_MPU_ALIGN))
340#endif
341#endif /* __CCAC__ */
342#endif /* CONFIG_ARC_MPU*/
343
344/* Typedef for the k_mem_partition attribute*/
346
347static ALWAYS_INLINE void arch_nop(void)
348{
349 __builtin_arc_nop();
350}
351
352#ifndef CONFIG_XIP
353extern char __arc_rw_sram_size[];
354#endif /* CONFIG_XIP */
355
356#endif /* _ASMLANGUAGE */
357
358#ifdef __cplusplus
359}
360#endif
361#endif /* ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_ */
static ALWAYS_INLINE void arch_nop(void)
Definition: arch.h:347
uint32_t k_mem_partition_attr_t
Definition: arch.h:225
#define ARCH_STACK_PTR_ALIGN
Definition: arch.h:98
ARCv2 public error handling.
ARCv2 public exception handling.
ARCv2 public kernel miscellaneous.
ARCv2 ARC Connect driver.
Per-arch thread definition.
ARCv2 public interrupt handling.
ARCv2 auxiliary registers definitions.
#define ALWAYS_INLINE
Definition: common.h:124
Devicetree main header.
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
Software-managed ISR table.