Zephyr Project API  3.4.0
A Scalable Open Source RTOS
cache.h
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1/*
2 * Copyright (c) 2015 Wind River Systems, Inc.
3 * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_CACHE_H_
9#define ZEPHYR_INCLUDE_CACHE_H_
10
16#include <zephyr/kernel.h>
17#include <zephyr/arch/cpu.h>
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#if defined(CONFIG_EXTERNAL_CACHE)
25
26#elif defined(CONFIG_ARCH_CACHE)
27#include <zephyr/arch/cache.h>
28
29#endif
30
42#define _CPU DT_PATH(cpus, cpu_0)
43
53{
54#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
55 cache_data_enable();
56#endif
57}
58
66{
67#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
68 cache_data_disable();
69#endif
70}
71
79{
80#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
81 cache_instr_enable();
82#endif
83}
84
92{
93#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
94 cache_instr_disable();
95#endif
96}
97
108{
109#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
110 return cache_data_flush_all();
111#endif
112 return -ENOTSUP;
113}
114
125{
126#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
127 return cache_instr_flush_all();
128#endif
129 return -ENOTSUP;
130}
131
142{
143#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
144 return cache_data_invd_all();
145#endif
146 return -ENOTSUP;
147}
148
159{
160#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
161 return cache_instr_invd_all();
162#endif
163 return -ENOTSUP;
164}
165
176{
177#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
178 return cache_data_flush_and_invd_all();
179#endif
180 return -ENOTSUP;
181}
182
193{
194#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
195 return cache_instr_flush_and_invd_all();
196#endif
197 return -ENOTSUP;
198}
199
212__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
213
214static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
215{
216#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
217 return cache_data_flush_range(addr, size);
218#endif
219 ARG_UNUSED(addr);
220 ARG_UNUSED(size);
221
222 return -ENOTSUP;
223}
224
237static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
238{
239#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
240 return cache_instr_flush_range(addr, size);
241#endif
242 ARG_UNUSED(addr);
243 ARG_UNUSED(size);
244
245 return -ENOTSUP;
246}
247
260__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
261
262static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
263{
264#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
265 return cache_data_invd_range(addr, size);
266#endif
267 ARG_UNUSED(addr);
268 ARG_UNUSED(size);
269
270 return -ENOTSUP;
271}
272
285static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
286{
287#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
288 return cache_instr_invd_range(addr, size);
289#endif
290 ARG_UNUSED(addr);
291 ARG_UNUSED(size);
292
293 return -ENOTSUP;
294}
295
308__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
309
310static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
311{
312#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
313 return cache_data_flush_and_invd_range(addr, size);
314#endif
315 ARG_UNUSED(addr);
316 ARG_UNUSED(size);
317
318 return -ENOTSUP;
319}
320
333static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
334{
335#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
336 return cache_instr_flush_and_invd_range(addr, size);
337#endif
338 ARG_UNUSED(addr);
339 ARG_UNUSED(size);
340
341 return -ENOTSUP;
342}
343
361{
362#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
363 return cache_data_line_size_get();
364#elif (CONFIG_DCACHE_LINE_SIZE != 0)
365 return CONFIG_DCACHE_LINE_SIZE;
366#else
367 return DT_PROP_OR(_CPU, d_cache_line_size, 0);
368#endif
369}
370
388{
389#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
390 return cache_instr_line_size_get();
391#elif (CONFIG_ICACHE_LINE_SIZE != 0)
392 return CONFIG_ICACHE_LINE_SIZE;
393#else
394 return DT_PROP_OR(_CPU, i_cache_line_size, 0);
395#endif
396}
397
398#ifdef CONFIG_LIBMETAL
399static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
400{
401 sys_cache_data_flush_range(addr, size);
402}
403#endif
404
405#include <syscalls/cache.h>
406#ifdef __cplusplus
407}
408#endif
409
414#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
#define ALWAYS_INLINE
Definition: common.h:124
static ALWAYS_INLINE int sys_cache_data_flush_all(void)
Flush the d-cache.
Definition: cache.h:107
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
Flush and Invalidate the i-cache.
Definition: cache.h:192
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
Get the the i-cache line size.
Definition: cache.h:387
static ALWAYS_INLINE void sys_cache_instr_disable(void)
Disable the i-cache.
Definition: cache.h:91
__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size)
Flush an address range in the d-cache.
__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size)
Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
Flush an address range in the i-cache.
Definition: cache.h:237
static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
Flush the i-cache.
Definition: cache.h:124
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
Get the the d-cache line size.
Definition: cache.h:360
__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the i-cache.
Definition: cache.h:333
static ALWAYS_INLINE void sys_cache_data_disable(void)
Disable the d-cache.
Definition: cache.h:65
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
Invalidate an address range in the i-cache.
Definition: cache.h:285
static ALWAYS_INLINE void sys_cache_data_enable(void)
Enable the d-cache.
Definition: cache.h:52
static ALWAYS_INLINE void sys_cache_instr_enable(void)
Enable the i-cache.
Definition: cache.h:78
static ALWAYS_INLINE int sys_cache_data_invd_all(void)
Invalidate the d-cache.
Definition: cache.h:141
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
Flush and Invalidate the d-cache.
Definition: cache.h:175
static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
Invalidate the i-cache.
Definition: cache.h:158
#define DT_PROP_OR(node_id, prop, default_value)
Like DT_PROP(), but with a fallback to default_value.
Definition: devicetree.h:772
#define ENOTSUP
Definition: errno.h:115
Public kernel APIs.