:orphan:
.. raw:: html
.. dtcompatible:: microchip,pic32ck-sg-gc-pll
.. _dtbinding_microchip_pic32ck_sg_gc_pll:
microchip,pic32ck-sg-gc-pll
###########################
.. sidebar:: Overview
:Name: ``microchip,pic32ck-sg-gc-pll``
:Vendor: :ref:`Microchip Technology Inc. `
:Used in: :zephyr:board-catalog:`List of boards <#compatibles=microchip,pic32ck-sg-gc-pll>` using
this compatible
Description
***********
.. code-block:: none
PIC32CK_SG_GC PLL clock
Phase Locked Loop (pll), 12.7 MHz to 200 MHz output frequency or up to 1.6 GHz for
fractional divider module use, from a 4 MHz to 48 MHz Reference Input Clock.
Properties
**********
Top level properties
====================
These property descriptions apply to "microchip,pic32ck-sg-gc-pll"
nodes themselves. This page also describes child node
properties in the following sections.
.. tabs::
.. group-tab:: Node specific properties
Properties not inherited from the base binding file.
(None)
.. group-tab:: Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
.. group-tab:: Base properties
Properties inherited from the base binding file, which defines
common properties that may be set on many nodes. Not all of these
may apply to the "microchip,pic32ck-sg-gc-pll" compatible.
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``status``
- ``string``
- .. code-block:: none
Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: ``okay``, ``disabled``, ``reserved``, ``fail``, ``fail-sss``
See :ref:`zephyr:dt-important-props` for more information.
* - ``compatible``
- ``string-array``
- .. code-block:: none
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is **required**.
See :ref:`zephyr:dt-important-props` for more information.
* - ``reg``
- ``array``
- .. code-block:: none
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
See :ref:`zephyr:dt-important-props` for more information.
* - ``reg-names``
- ``string-array``
- .. code-block:: none
Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
* - ``ranges``
- ``compound``
- .. code-block:: none
Information used to define a mapping (or translation) between the address
space of a bus (the "child address space") and the address space of the
bus node's parent (the "parent address space").
The "ranges" property is typically empty, or a sequence of triplets
(child bus address, parent bus address, length).
If the "ranges" property is empty, it specifies that the parent and child
address spaces are identical and no address translation is required.
If the "ranges" property is not present in a bus node, it is assumed that
no mapping exists between children of the node and the parent address space.
For details, see "2.3.8 ranges" in Devicetree Specification v0.4.
* - ``interrupts``
- ``array``
- .. code-block:: none
Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See :ref:`zephyr:dt-important-props` for more information.
* - ``interrupts-extended``
- ``compound``
- .. code-block:: none
Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
* - ``interrupt-names``
- ``string-array``
- .. code-block:: none
Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
* - ``interrupt-parent``
- ``phandle``
- .. code-block:: none
If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
* - ``label``
- ``string``
- .. code-block:: none
Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See :ref:`zephyr:dt-important-props` for more information.
* - ``clocks``
- ``phandle-array``
- .. code-block:: none
Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
* - ``clock-names``
- ``string-array``
- .. code-block:: none
Optional names given to each clock provider in the "clocks" property.
* - ``#address-cells``
- ``int``
- .. code-block:: none
This property encodes the number of cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
* - ``#size-cells``
- ``int``
- .. code-block:: none
This property encodes the number of cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
* - ``dma-coherent``
- ``boolean``
- .. code-block:: none
Indicates that the device is capable of coherent DMA operations.
For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
* - ``dmas``
- ``phandle-array``
- .. code-block:: none
DMA channel specifiers relevant to the device.
* - ``dma-names``
- ``string-array``
- .. code-block:: none
Optional names given to the DMA channel specifiers in the "dmas" property.
* - ``dma-ranges``
- ``compound``
- .. code-block:: none
The dma-ranges provides a means of defining a mapping or translation between the
physical address space of the bus and the physical address space of the parent of the bus.
For details, see "2.3.9 dma-ranges" in Devicetree Specification v0.4.
* - ``io-channels``
- ``phandle-array``
- .. code-block:: none
IO channel specifiers relevant to the device.
* - ``io-channel-names``
- ``string-array``
- .. code-block:: none
Optional names given to the IO channel specifiers in the "io-channels" property.
* - ``mboxes``
- ``phandle-array``
- .. code-block:: none
Mailbox / IPM channel specifiers relevant to the device.
* - ``mbox-names``
- ``string-array``
- .. code-block:: none
Optional names given to the mbox specifiers in the "mboxes" property.
* - ``power-domains``
- ``phandle-array``
- .. code-block:: none
Power domain specifiers relevant to the device.
* - ``power-domain-names``
- ``string-array``
- .. code-block:: none
Optional names given to the power domain specifiers in the "power-domains" property.
* - ``#power-domain-cells``
- ``int``
- .. code-block:: none
Number of cells in power-domains property
* - ``hwlocks``
- ``phandle-array``
- .. code-block:: none
HW spinlock id relevant to the device.
* - ``hwlock-names``
- ``string-array``
- .. code-block:: none
Optional names given to the hwlock specifiers in the "hwlocks" property.
* - ``zephyr,deferred-init``
- ``boolean``
- .. code-block:: none
Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
* - ``wakeup-source``
- ``boolean``
- .. code-block:: none
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
* - ``zephyr,pm-device-runtime-auto``
- ``boolean``
- .. code-block:: none
Automatically configure the device for runtime power management after the
init function runs.
* - ``zephyr,disabling-power-states``
- ``phandles``
- .. code-block:: none
List of power states that will disable this device power.
Child node properties
=====================
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``subsystem``
- ``int``
- .. code-block:: none
Clock subsystem
This property is **required**.
* - ``pll-enable``
- ``int``
- .. code-block:: none
Oscillator enable control.
0: to disable, 1: to enable
Default value: ``0``
Legal values: ``0``, ``1``
* - ``pll-on-demand-en``
- ``int``
- .. code-block:: none
On-demand oscillator control.
0: The oscillator is always on.
1: The oscillator is running when a peripheral is requesting the oscillator to be used as a
clock source. The oscillator is not running if no peripheral is requesting the clock source.
Important: Initializing it with 1, along with clock enabled, can lead to indefinite wait
for the clock to be on, if there is no peripheral request for the clock in the sequence of
clock Initialization. If required, better to turn on the clock using API, instead of
enabling both during startup.
Default value: ``0``
Legal values: ``0``, ``1``
* - ``pll-bandwidth-sel``
- ``string``
- .. code-block:: none
Select the pll0 closed loop filter bandwidth.
Depending on the frequency after the reference divider FPFD. Selecting the correct filter
bandwidth is important to operate the pll0'VCO in its best range.
Default value: ``bwsel-0``
Legal values: ``bwsel-0``, ``bwsel-1``, ``bwsel-2``, ``bwsel-3``, ``bwsel-4``, ``bwsel-5``, ``bwsel-6``, ``bwsel-7``
* - ``pll-src``
- ``string``
- .. code-block:: none
Reference clock source selection.
Selects the reference source clock for the PLL.
Default value: ``dfll48m``
Legal values: ``gclk0``, ``gclk1``, ``gclk2``, ``gclk3``, ``gclk4``, ``gclk5``, ``gclk6``, ``gclk7``, ``gclk8``, ``gclk9``, ``gclk10``, ``gclk11``, ``xosc``, ``dfll48m``
* - ``pll-feedback-divider-factor``
- ``int``
- .. code-block:: none
PLL feedback divider value.
This field determines the ratio of the pll0's VCO output frequency to the pll0 Reference
input frequency.
Writing to the FBDIV(feedback-divider-factor) bits will cause lock to be lost.
The value of FBDIV, (i.e. pll0FBDIV) must be within the range 21 ≤ FBDIV ≤ 1023.
The frequency of the Voltage Controlled Oscillator (VCO) giving the pll0 oscillation is
given by the formula: FVCO = FCKR * (FBDIV / REFDIV), (i.e., Must be between 800 MHz and
1600 MHz).
fCKR(source clock), REFDIV(ref-division-factor) and FBDIV must be selected to satisfy this
condition.
Default value: ``0``
* - ``pll-ref-division-factor``
- ``int``
- .. code-block:: none
PLL reference divider value.
This field determines the division factor of the pll0 input reference frequency.
Writing to the REFDIV bits will cause lock to be lost.
REFDIV value must be in the range of 1 ≤ REFDIV ≤ 63.
The frequency after the reference divider (FPFD) is given by the formula:
FPFD = FCKR / REFDIV (i.e., FPFD must always be between 4 MHz to 48 MHz).
Default value: ``0``
* - ``pll-freq-division-factor-int``
- ``int``
- .. code-block:: none
PLL frequency division factor integer part.
This field determines the ratio of the pll0's VCO output frequency to the pll0 Reference
input frequency.
Default value: ``0``
* - ``pll-freq-division-factor-rem``
- ``int``
- .. code-block:: none
PLL frequency division factor remainder part.
This field determines the ratio of the pll0's VCO output frequency to the pll0 Reference
input frequency.
Default value: ``0``
Grandchild node properties
==========================
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``subsystem``
- ``int``
- .. code-block:: none
Clock subsystem
This property is **required**.
* - ``pll-output-en``
- ``int``
- .. code-block:: none
PLL output enable control.
0: Output disabled
1: Output enabled
Default value: ``0``
Legal values: ``0``, ``1``
* - ``pll-output-division-factor``
- ``int``
- .. code-block:: none
PLL output division factor.
This field determines the division factor of the PLL0 FVCO output that
creates FCLK_PLL0 and CLK_PLL0_CLKOUTn.
The POSTDIV value must be between 1 ≤ POSTDIV ≤ 63.
Default value: ``0``