:orphan: .. raw:: html .. dtcompatible:: infineon,hppass-ac-state .. _dtbinding_infineon_hppass_ac_state: infineon,hppass-ac-state ######################## .. sidebar:: Overview :Name: ``infineon,hppass-ac-state`` :Vendor: :ref:`Infineon Technologies ` :Used in: :zephyr:board-catalog:`List of boards <#compatibles=infineon,hppass-ac-state>` using this compatible Description *********** .. code-block:: none Infineon HPPASS Autonomous Controller (AC) State Transition Table entry. Each node with this compatible represents one state in the AC State Transition Table (STT). The node is referenced by phandle from the parent HPPASS device's ac-states property, which determines the state's index in the table. This binding covers all STT fields: AC core, GPIO output, CSG (×5 slices), SAR, and SAR MUX (×4 channels). All properties default to 0, so only the fields relevant to a particular state need to be specified. Use constants from for condition, action, GPIO output, and SAR group mask values. Properties ********** .. tabs:: .. group-tab:: Node specific properties Properties not inherited from the base binding file. .. list-table:: :widths: 1 1 4 :header-rows: 1 * - Name - Type - Details * - ``ac-condition`` - ``int`` - .. code-block:: none AC condition code. Use IFX_HPPASS_AC_COND_* constants from . Default: FALSE (0). Default value: ``0`` * - ``ac-action`` - ``int`` - .. code-block:: none AC action code. Use IFX_HPPASS_AC_ACTION_* constants from . Default: STOP (0). Default value: ``0`` * - ``branch-state-idx`` - ``int`` - .. code-block:: none Branch target state index (0-15) within the ac-states list. Used when the action is BRANCH_IF_TRUE or BRANCH_IF_FALSE. Default value: ``0`` * - ``ac-interrupt`` - ``int`` - .. code-block:: none Interrupt/trigger flag (0 or 1). When set to 1, a pulse trigger or CPU interrupt is generated on entering this state (or after the wait condition is met for WAIT_FOR actions). Default value: ``0`` * - ``ac-count`` - ``int`` - .. code-block:: none Timer/counter value (1-4096). For WAIT_FOR actions this is an interval timer. For BRANCH_IF_* actions this is a loop counter. A value of 0 disables the timer/counter for this state. Default value: ``0`` * - ``gpio-out-unlock`` - ``int`` - .. code-block:: none GPIO output unlock flag (0 or 1). When 1, GPIO output mask is applied in this state. Default value: ``0`` * - ``gpio-out-msk`` - ``int`` - .. code-block:: none GPIO output mask. Use IFX_HPPASS_GPIO_OUT_* constants from . Can be OR'd for multiple outputs (e.g., GPIO_OUT_0 | GPIO_OUT_1). Default value: ``0`` * - ``csg0-unlock`` - ``int`` - .. code-block:: none CSG slice 0 unlock flag (0 or 1). Default value: ``0`` * - ``csg0-enable`` - ``int`` - .. code-block:: none CSG slice 0 enable flag (0 or 1). Requires csg0-unlock = 1. Default value: ``0`` * - ``csg0-dac-trig`` - ``int`` - .. code-block:: none CSG slice 0 DAC start/update trigger flag (0 or 1). Default value: ``0`` * - ``csg1-unlock`` - ``int`` - .. code-block:: none CSG slice 1 unlock flag (0 or 1). Default value: ``0`` * - ``csg1-enable`` - ``int`` - .. code-block:: none CSG slice 1 enable flag (0 or 1). Requires csg1-unlock = 1. Default value: ``0`` * - ``csg1-dac-trig`` - ``int`` - .. code-block:: none CSG slice 1 DAC start/update trigger flag (0 or 1). Default value: ``0`` * - ``csg2-unlock`` - ``int`` - .. code-block:: none CSG slice 2 unlock flag (0 or 1). Default value: ``0`` * - ``csg2-enable`` - ``int`` - .. code-block:: none CSG slice 2 enable flag (0 or 1). Requires csg2-unlock = 1. Default value: ``0`` * - ``csg2-dac-trig`` - ``int`` - .. code-block:: none CSG slice 2 DAC start/update trigger flag (0 or 1). Default value: ``0`` * - ``csg3-unlock`` - ``int`` - .. code-block:: none CSG slice 3 unlock flag (0 or 1). Default value: ``0`` * - ``csg3-enable`` - ``int`` - .. code-block:: none CSG slice 3 enable flag (0 or 1). Requires csg3-unlock = 1. Default value: ``0`` * - ``csg3-dac-trig`` - ``int`` - .. code-block:: none CSG slice 3 DAC start/update trigger flag (0 or 1). Default value: ``0`` * - ``csg4-unlock`` - ``int`` - .. code-block:: none CSG slice 4 unlock flag (0 or 1). Default value: ``0`` * - ``csg4-enable`` - ``int`` - .. code-block:: none CSG slice 4 enable flag (0 or 1). Requires csg4-unlock = 1. Default value: ``0`` * - ``csg4-dac-trig`` - ``int`` - .. code-block:: none CSG slice 4 DAC start/update trigger flag (0 or 1). Default value: ``0`` * - ``sar-unlock`` - ``int`` - .. code-block:: none SAR unlock flag (0 or 1). When 1, SAR enable state is applied in this state. Default value: ``0`` * - ``sar-enable`` - ``int`` - .. code-block:: none SAR enable flag (0 or 1). Requires sar-unlock = 1. Normally used with WAIT_FOR + BLOCK_READY condition. Default value: ``0`` * - ``sar-grp-msk`` - ``int`` - .. code-block:: none SAR sequencer group trigger mask. Use IFX_HPPASS_SAR_GRP_* constants from . Can be OR'd for multiple groups. Effective when SAR is enabled and SAR group trigger source is set to AC. Default value: ``0`` * - ``sar-mux0-unlock`` - ``int`` - .. code-block:: none SAR mux sampler 0 unlock flag (0 or 1). Default value: ``0`` * - ``sar-mux0-chan-idx`` - ``int`` - .. code-block:: none SAR mux sampler 0 channel selection (0-3). Default value: ``0`` * - ``sar-mux1-unlock`` - ``int`` - .. code-block:: none SAR mux sampler 1 unlock flag (0 or 1). Default value: ``0`` * - ``sar-mux1-chan-idx`` - ``int`` - .. code-block:: none SAR mux sampler 1 channel selection (0-3). Default value: ``0`` * - ``sar-mux2-unlock`` - ``int`` - .. code-block:: none SAR mux sampler 2 unlock flag (0 or 1). Default value: ``0`` * - ``sar-mux2-chan-idx`` - ``int`` - .. code-block:: none SAR mux sampler 2 channel selection (0-3). Default value: ``0`` * - ``sar-mux3-unlock`` - ``int`` - .. code-block:: none SAR mux sampler 3 unlock flag (0 or 1). Default value: ``0`` * - ``sar-mux3-chan-idx`` - ``int`` - .. code-block:: none SAR mux sampler 3 channel selection (0-3). Default value: ``0`` .. group-tab:: Deprecated node specific properties Deprecated properties not inherited from the base binding file. (None) .. group-tab:: Base properties Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the "infineon,hppass-ac-state" compatible. (None)