microchip,pic32cz-ca-dpll
Description
PIC32CZ_CA DPLL clock
Digital Phase Locked Loop (DPLL), 12.7 MHz to 300 MHz output frequency or up to 1.6 GHz for
fractional divider module use, from a 4 MHz to 48 MHz Reference Input Clock.
Properties
Top level properties
These property descriptions apply to “microchip,pic32cz-ca-dpll” nodes themselves. This page also describes child node properties in the following sections.
Node specific properties
Properties not inherited from the base binding file.
(None)
Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
Base properties
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “microchip,pic32cz-ca-dpll” compatible.
Name |
Type |
Details |
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
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This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
See Important properties for more information. |
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
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Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
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HW spinlock id relevant to the device.
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Optional names given to the hwlock specifiers in the "hwlocks" property.
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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Child node properties
Name |
Type |
Details |
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Clock subsystem
This property is required. |
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Select the PLL closed loop filter bandwidth.
Depending on the frequency after the reference divider FPFD. Selecting the correct filter
bandwidth is important to operate the PLL'VCO in its best range.
Default value: Legal values: |
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Reference source clock selection
Default value: Legal values: |
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0: The oscillator is always on
1: The oscillator is running when a peripheral is requesting the oscillator to be used as a
clock source. The oscillator is not running if no peripheral is requesting the clock source.
Important: Initializing it with 1, along with clock enabled, can lead to indefinite wait
for the clock to be on, if there is no peripheral request for the clock in the sequence of
clock Initialization. If required, better to turn on the clock using API, instead of
enabling both during startup.
Legal values: |
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Oscillator Enable
0: to disable, 1: to enable
Legal values: |
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This field determines the ratio of the PLL's VCO output frequency to the PLL Reference
input frequency.
Writing to the FBDIV(feedback-divider-factor) bits will cause lock to be lost.
The value of FBDIV, (i.e. PLLFBDIV) must be within the range 21 ≤ FBDIV ≤ 1023.
The frequency of the Voltage Controlled Oscillator (VCO) giving the PLL oscillation is
given by the formula: FVCO = FCKR * (FBDIV / REFDIV), (i.e., Must be between 800 MHz and
1600 MHz).
fCKR(source clock), REFDIV(ref-division-factor) and FBDIV must be selected to satisfy this
condition.
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This field determines the division factor of the PLL input reference frequency.
Writing to the REFDIV bits will cause lock to be lost.
REFDIV value must be in the range of 1 ≤ REFDIV ≤ 63.
The frequency after the reference divider (FPFD) is given by the formula:
FPFD = FCKR / REFDIV (i.e., FPFD must always be between 4 MHz to 48 MHz.
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Grandchild node properties
Name |
Type |
Details |
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Clock subsystem
This property is required. |
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0: Output disabled
1: Output enabled
Legal values: |
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This field determines the division factor of the PLL VCO frequency output.
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Fractional Frequency Divider integer part. Applicable only for PLL1 output 0 and 1.
Only the PLL1 supplies the clocks to the fractional dividers. FRACDIV0 is fed by PLL1
output 0 (under control of PLL1POSTDIVA[0]) and FRACDIV1 is fed by PLL1 output 1 (under
control of PLL1POSTDIVA[1]).
The maximum fractional divider input frequency is 1.6 GHz.
The divided frequency is given by the integer and reminder part of the divider, INTDIV and
REMDIV.
The resulting frequency FFRACDIV is calculated using the following equation:
FCLK_PLL1_FRC_CLKOUTn = FCLK_PLL/ (2 * (INTDIV + (REMDIV/ 512)))
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Fractional Frequency Divider reminder part. Applicable only for PLL1 output 0 and 1.
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