st,stm32g0-hsi-clock

Description

STM32 HSI Clock node description for STM32G0 devices
On STM32G0, HSI is a 16MHz fixed clock.

It also produces a HSISYS secondary clk which can be used as system clock
source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
SYSCLK = HSI16 / HSI DIV
      enum:
      - 1 ==> HSISYS = 16MHZ
      - 2 ==> HSISYS = 8MHZ
      - 4 ==> HSISYS = 4MHZ
      - 8 ==> HSISYS = 2MHZ
      - 16 ==> HSISYS = 1MHZ
      - 32 ==> HSISYS = 0.5MHz
      - 64 ==> HSISYS = 0.25MHZ
      - 128 ==> HSISYS = 0.125MHz

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

clock-frequency

int

output clock frequency (Hz)

This property is required.

hsi-div

int

HSI clock divider. Configures the output HSI clock frequency (HSISYS),
It does not apply to HSI clk selected as peripheral source clock
(eg: RNG clk driven by HSI)

This property is required.

Legal values: 1, 2, 4, 8, 16, 32, 64, 128