st,stm32l0-pll-clock

Vendor: STMicroelectronics N.V.

Description

STM32L0 and STM32L1 Main PLL node binding:

Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
input frequency from 2 to 24 MHz.

The desired PLL frequency can be computed with the following formula:

  f(PLL) = f(VCO clock) / PLLDIV  --> PLLCLK (System Clock)

    with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO

The PLL output frequency must not exceed 32 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div

int

 
PLL output division

This property is required.

Legal values: 2, 3, 4

mul

int

 
PLL multiplication factor for VCO
The PLL VCO clock frequency must not exceed:
- 96 MHz when the product is in Range 1
- 48 MHz when the product is in Range 2
- 24 MHz when the product is in Range 3
If the USB uses the PLL as clock source, the PLL VCO clock must be
programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).

This property is required.

Legal values: 3, 4, 6, 8, 12, 16, 24, 32, 48