st,stm32wba-pll-clock

Vendor: STMicroelectronics N.V.

Description

PLL node binding for STM32WBA devices

It can be used to describe PLL1

This PLL could take one of clk_hse or clk_hsi as input clock, with
an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

PLL1 can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formula:

  f(PLL_P) = f(VCO clock) / PLLP
  f(PLL_Q) = f(VCO clock) / PLLQ
  f(PLL_R) = f(VCO clock) / PLLR

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

Note: VCOx frequency range is 128 to 544 MHz. To reduce the power consumption,
      it is recommended to configure the VCO to the lowest frequency.

The PLL output frequency must not exceed 100 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div-m

int

 
Prescaler for PLLx
input clock
Valid range: 1 - 8

This property is required.

mul-n

int

 
PLLx multiplication factor for VCO
Valid range: 4 - 512

This property is required.

div-q

int

 
PLLx DIVQ division factor
Valid range: 1 - 128

div-r

int

 
PLLx DIVR division factor
Valid range: 1 - 128

This property is required.