andestech,andescore-v5

Vendor: Andes Technology Corporation

Description

Andes Technology RISC-V core from the AndesCore v5 series

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

 
Clock frequency in Hz

cpu-power-states

phandles

 
List of power management states supported by this cpu

i-cache-line-size

int

 
i-cache line size

d-cache-line-size

int

 
d-cache line size

enable-method

string

 
Enable method for cpu, either it is "psci" or "spin-table"

mmu-type

string

 
Memory Management Unit (MMU)

Legal values: 'riscv,sv32', 'riscv,sv39', 'riscv,sv48', 'riscv,none'

riscv,isa

string

 
RISC-V instruction set architecture

This property is required.