st,stm32-dma-v2
Vendor: STMicroelectronics N.V.
Note
An implementation of a driver matching this compatible is available in drivers/dma/dma_stm32.c.
Description
These nodes are “dma” bus nodes.
STM32 DMA controller (V2)
It is present on stm32 devices like stm32L4 or stm32WB.
This DMA controller includes several channels with different requests.
DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a four-cell specifier for each
capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a 3-cell specifier for each
channel: a phandle to the DMA controller plus the following four integer cells:
1. channel: the dma stream from 1 to <dma-requests>
2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
this value is 0 for Memory-to-memory transfers
or a value between <1> .. <dma-generators> (not supported yet)
or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
3. channel-config: A 32bit mask specifying the DMA channel configuration
A name custom DMA flags for channel configuration is used
which is device dependent. See stm32_dma.h:
-bit 5 : DMA cyclic mode config
0x0: STM32_DMA_MODE_NORMAL
0x1: STM32_DMA_MODE_CYCLIC
-bit 6-7 : Direction (see dma.h)
0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
0x3: reserved for PERIPH to PERIPH
-bit 9 : Peripheral Increment Address
0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
0x1: STM32_DMA_PERIPH_INC: increment address between transfers
-bit 10 : Memory Increment Address
0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
0x1: STM32_DMA_MEM_INC: increment address between transfers
-bit 11-12 : Peripheral data size
0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
0x3: reserved
-bit 13-14 : Memory data size
0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
0x3: reserved
-bit 15: Reserved
-bit 16-17 : Priority level
0x0: STM32_DMA_PRIORITY_LOW: low
0x1: STM32_DMA_PRIORITY_MEDIUM: medium
0x2: STM32_DMA_PRIORITY_HIGH: high
0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high
Example of dma usual combination for peripheral transfer
#define STM32_DMA_PERIPH_TX (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC)
#define STM32_DMA_PERIPH_RX (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC)
Example of dma node for stm32wb55x
dma2: dma-controller@40020400 {
compatible = "st,stm32-dma-v2";
...
dma-requests = <7>;
status = "disabled";
};
For the client part, example for stm32l476 on DMA1 instance
Tx using channel 3 with request 1
Rx using channel 2 with request 1
spi1 {
compatible = "st,stm32-spi";
dmas = <&dma1 3 1 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
<&dma1 2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
dma-names = "tx", "rx";
};
Properties
Node specific properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
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Number of items to expect in a DMA specifier
This property is required. Constant value: |
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If the DMA controller V1 supports memory to memory transfer
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offset in the table of channels when mapping to a DMAMUX
for 1st dma instance, offset is 0,
for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
plus the nb of dma channels of the 1st dma instance, etc.
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Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.
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Number of DMA channels supported by the controller
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Number of DMA request signals supported by the controller.
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Memory address alignment requirement for DMA buffers used by the controller.
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Memory size alignment requirement for DMA buffers used by the controller.
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Minimal chunk of data possible to be copied by the controller.
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Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
Base properties
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32-dma-v2” compatible.
Name |
Type |
Details |
|---|---|---|
|
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Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
|
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This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
|
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Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
|
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
|
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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Specifier cell names
dma cells: channel, slot, channel-config