tiac-magpie-pin-header

Vendor: Generic or vendor-independent

Description

GPIO pins exposed on TiaC MAGPIE headers.

The TiaC Magpie layout provides five headers, each two rows with
seven pins per row.

This binding provides a nexus mapping for 12 pins for each header,
left side pins are the odd pins numbered 0, 2, 4, 6, 8, 10, the right
side pins are the even pins numbered 1, 3, 5, 7, 9, 11. The bottom pins
on each side are used for ground, they are not mapped in the nexus.

         (GPIOx/1)  TMPHx/1  1 --o  o-- 2  TMPHx/2  (GPIOx/2)
         (GPIOx/3)  TMPHx/3  3 --o  o-- 4  TMPHx/4  (GPIOx/4)
         (GPIOx/5)  TMPHx/5  5 --o  o-- 6  TMPHx/6  (GPIOx/6)
         (GPIOx/7)  TMPHx/7  7 --o  o-- 8  TMPHx/8  (GPIOx/8)
         (GPIOx/9)  TMPHx/9  9 --o  o-- 10 TMPHx/10 (GPIOx/10)
        (GPIOx/12) TMPHx/11 11 --o  o-- 12 TMPHx/12 (GPIOx/12)
             (GND)          13 --o  o-- 14          (GND)

Board's silkscreen may vary depending your board, but coherent with the
description above as it's according to the standard's specification.
Not every TiaC board provides all five headers.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

gpio-map

compound

This property is required.

gpio-map-mask

compound

gpio-map-pass-thru

compound

#gpio-cells

int

Number of items to expect in a GPIO specifier

This property is required.