cypress,psoc6-intmux

Vendor: Cypress Semiconductor Corporation

Description

Cypress Interrupt Multiplex

The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
user can select up to 32 interrupts sources from the 240 possible vectors
to be processed in the Cortex-M0+ CPU.

At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to
configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
4 interrupt sources by grouping intmux channels. These means that each byte
from intmux[0~7] store a 'vector number' which selects the peripheral
interrupt source in the multiplexer. The multiplexer is placed before
Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
directly connected to NVIC and doesn't require any special configuration.

On a general view, the below represents the Interrupt Multiplexer
configuration and how the Cortex-M0+ NVIC sources are organized. Each
channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
The vector number selects the PSOC 6 peripheral interrupt source for the
Cortex-M0+ NVIC controller line.

intmux[0] = {ch03, ch02, ch01, ch00}
intmux[1] = {ch07, ch06, ch05, ch04}
...
intmux[7] = {ch31, ch30, ch29, ch28}

In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
sources and the proper NVIC interrupt order. With that, the system configures
the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
More information about it at PSOC 6 Architecture Technical Reference Manual,
section CPU Sub System (CPUSS) Registers.


The below fragment configure the GPIO Port 0 to generate an interrupt at
Cortex-M0+ NVIC:

At psoc6.dtsi file the gpio_prt0 peripheral had the interrupt source 2:

gpio_prt0: gpio@40320100 {
  interrupts = <2 1>;
};

In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
must be defined at gpio_prt0 node selecting the Interrupt Multiplex Channel.
This can be defined at <board>_m0.dts file:

&gpio_prt0 {
  interrupt-parent = <&intmux_ch20>;
};

The translation of these two definitions is:
       CH   REGS  INT NUM    CH   CH/REG
intmux[20 mod 8] |= 0x02 << (20 mod 4);

These results in Cortex-M0+ NVIC line 20 handling PSOC 6 interrupt source 2.
The interrupt can be enabled/disabled at NVIC at line 20 as usual.

Notes:
1) Multiple definitions will generate multiple interrupts
2) The interrupt sources are shared between Cortex-M0+/M4. This means, they
   can trigger actions in parallel on both processors.
3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
   at interrupt-parent properties.
4) Only the peripherals used by Cortex-M0+ should be configured.

Properties

Node specific properties

Properties not inherited from the base binding file.

(None)

Deprecated node specific properties

Deprecated properties not inherited from the base binding file.

(None)

Base properties

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “cypress,psoc6-intmux” compatible.

Name	Type	Details
reg	array	register space This property is required. See Important properties for more information.
status	string	indicates the operational status of a device Legal values: 'ok', 'okay', 'disabled', 'reserved', 'fail', 'fail-sss' See Important properties for more information.
compatible	string-array	compatible strings This property is required. See Important properties for more information.
reg-names	string-array	name of each register space
interrupts	array	interrupts for device See Important properties for more information.
interrupts-extended	compound	extended interrupt specifier for device
interrupt-names	string-array	name of each interrupt
interrupt-parent	phandle	phandle to interrupt controller node
label	string	Human readable string describing the device (used as device_get_binding() argument) See Important properties for more information. This property is deprecated.
clocks	phandle-array	Clock gate information
clock-names	string-array	name of each clock
#address-cells	int	number of address cells in reg property
#size-cells	int	number of size cells in reg property
dmas	phandle-array	DMA channels specifiers
dma-names	string-array	Provided names of DMA channel specifiers
io-channels	phandle-array	IO channels specifiers
io-channel-names	string-array	Provided names of IO channel specifiers
mboxes	phandle-array	mailbox / IPM channels specifiers
mbox-names	string-array	Provided names of mailbox / IPM channel specifiers
power-domains	phandle-array	Power domain specifiers
power-domain-names	string-array	Provided names of power domain specifiers
#power-domain-cells	int	Number of cells in power-domains property
zephyr,deferred-init	boolean	Do not initialize device automatically on boot. Device should be manually initialized using device_init().
wakeup-source	boolean	Property to identify that a device can be used as wake up source. When this property is provided a specific flag is set into the device that tells the system that the device is capable of wake up the system. Wake up capable devices are disabled (interruptions will not wake up the system) by default but they can be enabled at runtime if necessary.
zephyr,pm-device-runtime-auto	boolean	Automatically configure the device for runtime power management after the init function runs.
zephyr,disabling-power-states	phandles	List of power states that will disable this device power.