renesas,smartbond-nor-psram
Vendor: Renesas Electronics Corporation
Note
An implementation of a driver matching this compatible is available in drivers/memc/memc_smartbond_nor_psram.c.
Description
Renesas Smartbond(tm) NOR/PSRAM controller
Properties
Node specific properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
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If present, the memory controller will be configured to drive PSRAM devices.
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Memory size/capacity in bits.
This property is required. |
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Device type, part of device ID, used to verify the memory device used.
This property is required. |
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Device density, part of device ID, used to verify the memory device used.
[7:0] should reflect the density value itself and [15:8] should reflect
the mask that should be applied to the returned device ID value.
This is because part of its byte value might contain invalid bits.
This property is required. |
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Manufacturer ID, part of device ID, used to verify the memory device used.
This property is required. |
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Time in microseconds (us) the memory device can accept the next command following a SW reset.
This property is required. |
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Min. time, in nanoseconds, the #CS line should remain inactive between
the transmission of two different instructions.
This property is required. |
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Min. time, in nanoseconds, the #CS line should remain inactive after the execution
of a write enable, erase, erase suspend or erase resume instruction. This setting
is not used if is-ram property is present.
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Command to enter the QPI mode supported by a memory device
(should be transmitted in single bus mode).
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Command to exit the QPI mode supported by a memory device
(should be transmitted in quad bus mode).
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If present, the memory device will enter the QPI mode which typically reflects that
all bytes be sent in quad bus mode. It's a pre-requisite that read and write
commands, that should be read-cmd and write-cmd respectively, reflect the QPI mode.
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Read command for single/burst read accesses in auto mode. Default value is the opcode
for single mode which is supported by all memory devices.
Default value: |
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Write command for single/burst write accesses in auto mode. Default value is the opcode
for single mode which is supported by all memory devices.
Default value: |
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Clock mode when #CS is idle/inactive
- Mode0: #CLK is low when #CS is inactive
- Mode3: #CLK is high when #CS is inactive
Mode0 is selected by default as it should be supported by all memory devices.
Default value: Legal values: |
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Address size to use in auto mode. In 24-bit mode up to 16MB can be
accessed whilst in 32-bit mode up to 32MB can be accessed which is
the max. address space supported by QSPICx. Default value is 24-bit
mode which is supported by all memory devices.
Default value: Legal values: |
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Clock divider for QSPIC2 controller. The clock path of
this block is always DIV1 which reflects the current
system clock.
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If a non zero value is applied, then Tcem should be taken into
consideration by QSPIC2 so that it can split a burst read/write
access in case the total time exceeds the defined value
(at the cost of extra cycles required for re-sending the instruction,
address and dummy bytes, if any). This setting is meaningful only if
is-ram is present. This value reflects the max. time in microseconds
the #CS line can be driven low in a write/read burst access
(required for the auto-refresh mechanism, when supported).
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Number of dummy bytes to send for single/burst read access in auto mode.
This property is required. Legal values: |
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If present, the extra byte will be sent after the dummy bytes, if any.
This should be useful if 3 dummy bytes are required. In such a case,
dummy-bytes-count should be set to 2.
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Extra byte to be sent, if extra-byte-enable is present.
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Describes the mode of SPI bus during the address phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the instruction phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the data phase for single/burst
read accesses in auto mode. Default value is single mode which should
be supported by all memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the dummy bytes phase for single/burst
read accesses in auto mode. The single mode should be supported by all
memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the extra byte phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.
Legal values: |
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Describes the mode of SPI bus during the address phase for single/burst
write accesses in auto mode. Default value is single mode which should
be supported by all memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the instruction phase for single/burst
write accesses in auto mode. The single mode should be supported by all
memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the data phase for single/burst
write accesses in auto mode. Default value is single mode which should
be supported by all memory devices.
Default value: Legal values: |
Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
Base properties
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “renesas,smartbond-nor-psram” compatible.
Name |
Type |
Details |
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Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
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This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
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Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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