renesas,smartbond-nor-psram
Vendor: Renesas Electronics Corporation
Description
Renesas Smartbond(tm) NOR/PSRAM controller
Properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
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If present, the memory controller will be configured to drive PSRAM devices.
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Memory size/capacity in bits.
This property is required. |
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Device type, part of device ID, used to verify the memory device used.
This property is required. |
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Device density, part of device ID, used to verify the memory device used.
[7:0] should reflect the density value itself and [15:8] should reflect
the mask that should be applied to the returned device ID value.
This is because part of its byte value might contain invalid bits.
This property is required. |
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Manufacturer ID, part of device ID, used to verify the memory device used.
This property is required. |
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Time in microseconds (us) the memory device can accept the next command following a SW reset.
This property is required. |
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Min. time, in nanoseconds, the #CS line should remain inactive between
the transmission of two different instructions.
This property is required. |
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Min. time, in nanoseconds, the #CS line should remain inactive after the execution
of a write enable, erase, erase suspend or erase resume instruction. This setting
is not used if is-ram property is present.
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Command to enter the QPI mode supported by a memory device
(should be transmitted in single bus mode).
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Command to exit the QPI mode supported by a memory device
(should be transmitted in quad bus mode).
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If present, the memory device will enter the QPI mode which typically reflects that
all bytes be sent in quad bus mode. It's a pre-requisite that read and write
commands, that should be read-cmd and write-cmd respectively, reflect the QPI mode.
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Read command for single/burst read accesses in auto mode. Default value is the opcode
for single mode which is supported by all memory devices.
Default value: |
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Write command for single/burst write accesses in auto mode. Default value is the opcode
for single mode which is supported by all memory devices.
Default value: |
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Clock mode when #CS is idle/inactive
- Mode0: #CLK is low when #CS is inactive
- Mode3: #CLK is high when #CS is inactive
Mode0 is selected by default as it should be supported by all memory devices.
Default value: Legal values: |
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Address size to use in auto mode. In 24-bit mode up to 16MB can be
accessed whilst in 32-bit mode up to 32MB can be accessed which is
the max. address space supported by QSPICx. Default value is 24-bit
mode which is supported by all memory devices.
Default value: Legal values: |
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Clock divider for QSPIC2 controller. The clock path of
this block is always DIV1 which reflects the current
system clock.
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If a non zero value is applied, then Tcem should be taken into
consideration by QSPIC2 so that it can split a burst read/write
access in case the total time exceeds the defined value
(at the cost of extra cycles required for re-sending the instruction,
address and dummy bytes, if any). This setting is meaningful only if
is-ram is present. This value reflects the max. time in microseconds
the #CS line can be driven low in a write/read burst access
(required for the auto-refresh mechanism, when supported).
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Number of dummy bytes to send for single/burst read access in auto mode.
This property is required. Legal values: |
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If present, the extra byte will be sent after the dummy bytes, if any.
This should be useful if 3 dummy bytes are required. In such a case,
dummy-bytes-count should be set to 2.
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Extra byte to be sent, if extra-byte-enable is present.
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Describes the mode of SPI bus during the address phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the instruction phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the data phase for single/burst
read accesses in auto mode. Default value is single mode which should
be supported by all memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the dummy bytes phase for single/burst
read accesses in auto mode. The single mode should be supported by all
memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the extra byte phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.
Legal values: |
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Describes the mode of SPI bus during the address phase for single/burst
write accesses in auto mode. Default value is single mode which should
be supported by all memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the instruction phase for single/burst
write accesses in auto mode. The single mode should be supported by all
memory devices.
Default value: Legal values: |
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Describes the mode of SPI bus during the data phase for single/burst
write accesses in auto mode. Default value is single mode which should
be supported by all memory devices.
Default value: Legal values: |
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “renesas,smartbond-nor-psram” compatible.
Name |
Type |
Details |
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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register space
This property is required. See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. This property is deprecated. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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