st,stm32-fmc-nor-psram
Vendor: STMicroelectronics N.V.
Note
An implementation of a driver matching this compatible is available in drivers/memc/memc_stm32_nor_psram.c.
Description
STM32 Flexible Memory Controller (NOR Flash/PSRAM/SRAM controller).
The FMC generates the appropriate signal timings to drive the
following types of memories:
* Asynchronous SRAM and ROM
- 8 bits
- 16 bits
- 32 bits
* PSRAM (Cellular RAM)
- Asynchronous mode
- Burst mode for synchronous accesses with configurable option to split burst
access when crossing boundary page for CRAM 1.5.
- Multiplexed or non-multiplexed
* NOR Flash memory
- Asynchronous mode
- Burst mode for synchronous accesses
- Multiplexed or non-multiplexed
A unique Chip Select signal (NE) is used per bank. All the other
signals (addresses, data and control) are shared. A wide range of
devices is supported through programmable timings.
Refer to the reference manual for more details.
The FMC NOR/PSRAM controller is defined below the FMC node and banks are
defined as child nodes of the FMC NOR/PSRAM controller node.
You can enable the controller in devicetree as follows:
&fmc {
status = "okay";
pinctrl-0 = <&fmc_nwe_pd5 &fmc_noe_pd4 ...>;
pinctrl-names = "default";
sram {
status = "okay";
compatible = "st,stm32-fmc-nor-psram";
#address-cells = <1>;
#size-cells = <0>;
sram2@2 {
reg = <0x2>;
st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
STM32_FMC_MEMORY_TYPE_SRAM
STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
STM32_FMC_BURST_ACCESS_MODE_DISABLE
STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
STM32_FMC_WAIT_TIMING_BEFORE_WS
STM32_FMC_WRITE_OPERATION_ENABLE
STM32_FMC_WAIT_SIGNAL_DISABLE
STM32_FMC_EXTENDED_MODE_DISABLE
STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
STM32_FMC_WRITE_BURST_DISABLE
STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
STM32_FMC_WRITE_FIFO_DISABLE
STM32_FMC_PAGE_SIZE_NONE>;
st,timing = <4 2 3 0 16 17 STM32_FMC_ACCESS_MODE_A>;
};
};
};
Use constants defined in dt-bindings/memory-controller/stm32-fmc-nor-psram.h.
Properties
Top level properties
These property descriptions apply to “st,stm32-fmc-nor-psram” nodes themselves. This page also describes child node properties in the following sections.
Node specific properties
Properties not inherited from the base binding file.
(None)
Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
Base properties
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32-fmc-nor-psram” compatible.
Name |
Type |
Details |
|---|---|---|
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
This property is required. Constant value: |
|
|
This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
This property is required. |
|
|
Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
|
|
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
See Important properties for more information. |
|
|
Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
|
|
|
Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
|
|
Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
|
|
Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
|
|
|
Optional names given to each clock provider in the "clocks" property.
|
|
|
DMA channel specifiers relevant to the device.
|
|
|
Optional names given to the DMA channel specifiers in the "dmas" property.
|
|
|
IO channel specifiers relevant to the device.
|
|
|
Optional names given to the IO channel specifiers in the "io-channels" property.
|
|
|
Mailbox / IPM channel specifiers relevant to the device.
|
|
|
Optional names given to the mbox specifiers in the "mboxes" property.
|
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Power domain specifiers relevant to the device.
|
|
|
Optional names given to the power domain specifiers in the "power-domains" property.
|
|
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Number of cells in power-domains property
|
|
|
Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
|
|
|
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
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|
Automatically configure the device for runtime power management after the
init function runs.
|
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|
List of power states that will disable this device power.
|
Child node properties
Name |
Type |
Details |
|---|---|---|
|
|
This property is required. See Important properties for more information. |
|
|
SRAM/NOR-Flash control register (FMC_BCRx).
Contains control information of each memory bank,
used for SRAMs, PSRAM and NOR Flash memories.
Expected fields, in order:
* MUXEN - Address/data multiplexing enable bit.
* MTYP - Memory type.
* MWID - Memory data bus width.
* FACCEN - Flash access enable.
* BURSTEN - Burst enable bit.
* WAITPOL - Wait signal polarity bit.
* WAITCFG - Wait timing configuration.
* WREN - Write enable bit.
* WAITEN - Wait enable bit.
* EXTMOD - Extended mode enable.
If set, then 'st,timing-ext' shall be provided.
* ASYNCWAIT - Wait signal during asynchronous transfers.
* CPSIZE - Cellular RAM (CRAM) 1.5 Page Size.
* CBURSTRW - Write burst enable.
* CCLKEN - Continuous Clock Enable.
* WFDIS - Write FIFO Disable.
* BMAP - FMC bank mapping.
This property is required. |
|
|
SRAM/NOR-Flash (read) timing register (FMC_BTRx).
If the EXTMOD is set (see control register FMC_BCRx), then
FMC_BTRx register is partitioned for write and read access.
That means, use this property to configure read accesses and
'st,timing-ext' to configure write accesses.
Expected fields, in order:
* ADDSET - Address setup phase duration.
Number of HCLK cycles to configure the duration of
the address setup time. This parameter can be a value
between Min_Data = 0 and Max_Data = 15.
Note: Not used with synchronous NOR Flash memories.
* ADDHLD - Address-hold phase duration.
Number of HCLK cycles to configure the duration of
the address hold time. This parameter can be a value
between Min_Data = 1 and Max_Data = 15.
Note: Not used with synchronous NOR Flash memories.
* DATAST - Data-phase duration.
Number of HCLK cycles to configure the duration of
the data setup time. This parameter can be a value
between Min_Data = 1 and Max_Data = 255.
Note: Used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories.
* BUSTURN - Bus turnaround phase duration.
Number of HCLK cycles to configure the duration of
the bus turnaround. This parameter can be a value
between Min_Data = 0 and Max_Data = 15.
Note: Only used for multiplexed NOR Flash memories.
* CLKDIV - Clock divide ratio (for FMC_CLK signal).
Period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value
between Min_Data = 2 and Max_Data = 16.
Note: Not used for asynchronous NOR Flash, SRAM or ROM
accesses.
* DATLAT - Data latency for synchronous memory.
Number of memory clock cycles to issue to the memory
before getting the first data.
The value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17
in NOR Flash memories with synchronous burst mode enable
* ACCMOD - Access mode.
See access mode defines
in dt-bindings/memory-controller/stm32-fmc-nor-psram.h.
This property is required. |
|
|
SRAM/NOR-Flash (write) timing register (FMC_BWTRx).
Expected fields, in order:
* ADDSET - Address setup phase duration.
Reset state: 15 (0xF).
* ADDHLD - Address-hold phase duration.
Reset state: 15 (0xF).
* DATAST - Data-phase duration.
Reset state: 255 (0xFF).
* BUSTURN - Bus turnaround phase duration.
Reset state: 15 (0xF).
* ACCMOD - Access mode.
Reset state: 0 (0x0).
Refer to 'st,timing' for detailed field descriptions.
This property is applied only when EXTMOD is set
(see control register FMC_BCRx).
If absent, then reset state values are used.
Default value: |