st,stm32-fmc-sdram

Vendor: STMicroelectronics N.V.

Note

An implementation of a driver matching this compatible is available in drivers/memc/memc_stm32_sdram.c.

Description

STM32 Flexible Memory Controller (SDRAM controller).

The FMC SDRAM controller can be used to interface with external SDRAM
memories. Up to 2 SDRAM banks are supported with independent configuration. It
is worth to note that while settings are independent, some are shared or are
required to be set according to the most constraining device. Refer to the
properties description or the datasheet for more details.

The FMC SDRAM controller is defined below the FMC node and SDRAM banks are
defined as child nodes of the FMC SDRAM node. You can either have bank 1 (@0),
bank 2 (@1) or both. You can enable the FMC SDRAM controller in your board
DeviceTree file like this:

&fmc {
    status = "okay";
    pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;

    sdram {
        status = "okay";

        power-up-delay = <100>;
        num-auto-refresh = <8>;
        mode-register = <0x220>;
        refresh-rate = <603>;

        bank@0 {
            reg = <0>;

            st,sdram-control = <STM32_FMC_SDRAM_NC_9
                                STM32_FMC_SDRAM_NR_12
                                STM32_FMC_SDRAM_MWID_32
                                STM32_FMC_SDRAM_NB_4
                                STM32_FMC_SDRAM_CAS_2
                                STM32_FMC_SDRAM_SDCLK_PERIOD_2
                                STM32_FMC_SDRAM_RBURST_ENABLE
                                STM32_FMC_SDRAM_RPIPE_0>;
            st,sdram-timing = <2 6 4 6 2 2 2>;
        };

        bank@1 {
            reg = <1>;
            ...
        };
    };
};

Note that you will find definitions for the st,sdram-control field at
dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
in the SoC DeviceTree files.

Finally, in order to make the memory available you will need to define new
memory device/s in DeviceTree:

sdram1: sdram@c0000000 {
    compatible = "zephyr,memory-region", "mmio-sram";
    device_type = "memory";
    reg = <0xc0000000 DT_SIZE_M(X)>;
    zephyr,memory-region = "SDRAM1";
};

sdram2: sdram@d0000000 {
    compatible = "zephyr,memory-region", "mmio-sram";
    device_type = "memory";
    reg = <0xd0000000 DT_SIZE_M(X)>;
    zephyr,memory-region = "SDRAM2";
};

It is important to use sdram1 and sdram2 node labels for bank 1 and bank 2
respectively. Memory addresses are 0xc0000000 and 0xd0000000 for bank 1 and
bank 2 respectively.

Properties

Top level properties

These property descriptions apply to “st,stm32-fmc-sdram” nodes themselves. This page also describes child node properties in the following sections.

Node specific properties

Properties not inherited from the base binding file.

Name

Type

Details

power-up-delay

int

 
Power-up delay in microseconds.

Default value: 100

num-auto-refresh

int

 
Number of auto-refresh commands issued.

Default value: 8

mode-register

int

 
A 14-bit field that defines the SDRAM Mode Register content. The mode register bits are also used to program the extended mode register for mobile SDRAM.

This property is required.

refresh-rate

int

 
A 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles.

This property is required.

Deprecated node specific properties

Deprecated properties not inherited from the base binding file.

(None)

Base properties

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32-fmc-sdram” compatible.

Name

Type

Details

#address-cells

int

 
This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.

For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.

This property is required.

Constant value: 1

#size-cells

int

 
This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.

For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.

This property is required.

status

string

 
Indicates the operational status of the hardware or other
resource that the node represents. In particular:

  - "okay" means the resource is operational and, for example,
    can be used by device drivers
  - "disabled" means the resource is not operational and the system
    should treat it as if it is not present

For details, see "2.3.4 status" in Devicetree Specification v0.4.

Legal values: 'ok', 'okay', 'disabled', 'reserved', 'fail', 'fail-sss'

See Important properties for more information.

compatible

string-array

 
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.

The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.

The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.

For details, see "2.3.1 compatible" in Devicetree Specification v0.4.

This property is required.

See Important properties for more information.

reg

array

 
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).

The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.

For details, see "2.3.6 reg" in Devicetree Specification v0.4.

See Important properties for more information.

reg-names

string-array

 
Optional names given to each register block in the "reg" property.
For example:

  / {
       soc {
           #address-cells = <1>;
           #size-cells = <1>;

           uart@1000 {
               reg = <0x1000 0x2000>, <0x3000 0x4000>;
               reg-names = "foo", "bar";
           };
       };
  };

The uart@1000 node has two register blocks:

  - one with base address 0x1000, size 0x2000, and name "foo"
  - another with base address 0x3000, size 0x4000, and name "bar"

interrupts

array

 
Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

See Important properties for more information.

interrupts-extended

compound

 
Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

interrupt-names

string-array

 
Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

interrupt-parent

phandle

 
If present, this refers to the node which handles interrupts generated
by this device.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

label

string

 
Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.

For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.

See Important properties for more information.

clocks

phandle-array

 
Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:

  https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

clock-names

string-array

 
Optional names given to each clock provider in the "clocks" property.

dmas

phandle-array

 
DMA channel specifiers relevant to the device.

dma-names

string-array

 
Optional names given to the DMA channel specifiers in the "dmas" property.

io-channels

phandle-array

 
IO channel specifiers relevant to the device.

io-channel-names

string-array

 
Optional names given to the IO channel specifiers in the "io-channels" property.

mboxes

phandle-array

 
Mailbox / IPM channel specifiers relevant to the device.

mbox-names

string-array

 
Optional names given to the mbox specifiers in the "mboxes" property.

power-domains

phandle-array

 
Power domain specifiers relevant to the device.

power-domain-names

string-array

 
Optional names given to the power domain specifiers in the "power-domains" property.

#power-domain-cells

int

 
Number of cells in power-domains property

zephyr,deferred-init

boolean

 
Do not initialize device automatically on boot. Device should be manually
initialized using device_init().

wakeup-source

boolean

 
Property to identify that a device can be used as wake up source.

When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.

Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.

zephyr,pm-device-runtime-auto

boolean

 
Automatically configure the device for runtime power management after the
init function runs.

zephyr,disabling-power-states

phandles

 
List of power states that will disable this device power.

Child node properties

Name

Type

Details

reg

int

This property is required.

See Important properties for more information.

st,sdram-control

array

 
SDRAM control configuration. Expected fields, in order, are,

- NC: Number of bits of a column address.
- NR: Number of bits of a row address.
- MWID: Memory device width.
- NB: Number of internal banks.
- CAS: SDRAM CAS latency in number of memory clock cycles.
- SDCLK: SDRAM clock period. If two SDRAM devices are used both should
  have the same value.
- RBURST: Enable burst read mode. If two SDRAM devices are used both
  should have the same value.
- RPIPE: Delay, in fmc_ker_ck clock cycles, for reading data after CAS
  latency. If two SDRAM devices are used both should have the same
  value.

This property is required.

st,sdram-timing

array

 
SDRAM timing configuration. Expected fields, in order, are,

- TMRD: Delay between a Load Mode Register command and an Active or
  Refresh command in number of memory clock cycles.
- TXSR: Delay from releasing the Self-refresh command to issuing the
  Activate command in number of memory clock cycles. If two SDRAM
  devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with
  the same TXSR timing corresponding to the slowest SDRAM device
- TRAS: Minimum Self-refresh period in number of memory clock cycles.
- TRC: Delay between the Refresh command and the Activate command, as
  well as the delay between two consecutive Refresh commands. It is
  expressed in number of memory clock cycles. If two SDRAM devices are
  used, the TRC must be programmed with the timings of the slowest
  device in both banks.
- TWP: Delay between a Write and a Precharge command in number of memory
  clock cycles
- TRP: Delay between a Precharge command and another command in number
  of memory clock cycles. If two SDRAM devices are used, the TRP must be
  programmed with the timing of the slowest device in both banks.
- TRCD: Delay between the Activate command and a Read/Write command in
  number of memory clock cycles.

This property is required.