sipo-mux-gp-spi (on spi bus)

Vendor: Generic or vendor-independent

Description

Generic latched SIPO/MUX GP matrix controller, SPI binding

Driver bindings for controlling a latched SIPO/MUX General
Purpose (GP) matrix with a SPI master.

The SPI driver should be usable as long as a Zephyr SPI API
driver is available for your board. Hardware specific tuning
is required using these properties:

  - spi-max-frequency

Properties

Properties not inherited from the base binding file.

Name

Type

Details

supply-gpios

phandle-array

 
GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

 
Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

spi-max-frequency

int

 
Maximum clock frequency of device's SPI interface in Hz

This property is required.

duplex

int

 
Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0    SPI_FULL_DUPLEX
  2048 SPI_HALF_DUPLEX

Legal values: 0, 2048

frame-format

int

 
Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0     SPI_FRAME_FORMAT_MOTOROLA
  32768 SPI_FRAME_FORMAT_TI

Legal values: 0, 32768

spi-cpol

boolean

 
SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.

spi-cpha

boolean

 
SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.

spi-hold-cs

boolean

 
In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.

shift-width

int

 
Width of columns bits totally shifted out by the SIPO shift register.
This value must be equal or greater then the data width.

This property is required.

Legal values: 8, 16, 24, 32

data-width

int

 
Width of columns data bits shifted out by the SIPO shift register and
usable on hardware in reality.

This property is required.

Legal values: 8, 16, 24, 32

addr-gpios

phandle-array

 
GPIO phandle and specifier for the pins connected to the rows
address MUX decoder pins. At least one pin should be given for
a single or two rows. Pins of multiples of two should be given
for more rows.

This property is required.

oe-gpios

phandle-array

 
GPIO phandle and specifier for the pin connected to the columns
data SIPO shift register's output enable pin. Exactly one pin
should be given.

This property is required.

refresh-time-us

int

 
How often to iterate over the addresses and refresh the data
signal lines.

Default value: 1000