ambiq,apollo3-pinctrl

Description

The Ambiq Apollo3 pin controller is a node responsible for controlling
pin function selection and pin properties, such as routing a UART0 TX
to pin 60 and enabling the pullup resistor on that pin.

The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this:

&pinctrl {
  /* your modifications go here */
};

All device pin configurations should be placed in child nodes of the
'pinctrl' node, as shown in this example:

/* You can put this in places like a board-pinctrl.dtsi file in
 * your board directory, or a devicetree overlay in your application.
*/

/* include pre-defined combinations for the SoC variant used by the board */
#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>

&pinctrl {
  uart0_default: uart0_default {
    group1 {
      pinmux = <UART0TX_P60>;
    };
    group2 {
      pinmux = <UART0RX_P47>;
      input-enable;
    };
  };
};

The 'uart0_default' child node encodes the pin configurations for a
particular state of a device; in this case, the default (that is, active)
state.

As shown, pin configurations are organized in groups within each child node.
Each group can specify a list of pin function selections in the 'pinmux'
property.

A group can also specify shared pin properties common to all the specified
pins, such as the 'input-enable' property in group 2.

Properties

Top level properties

These property descriptions apply to “ambiq,apollo3-pinctrl” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “ambiq,apollo3-pinctrl” compatible.

Name	Type	Details
`wakeup-source`	`boolean`	Property to identify that a device can be used as wake up source. When this property is provided a specific flag is set into the device that tells the system that the device is capable of wake up the system. Wake up capable devices are disabled (interruptions will not wake up the system) by default but they can be enabled at runtime if necessary.
`power-domain`	`phandle`	Power domain the device belongs to. The device will be notified when the power domain it belongs to is either suspended or resumed.
`zephyr,pm-device-runtime-auto`	`boolean`	Automatically configure the device for runtime power management after the init function runs.
`zephyr,disabling-power-states`	`phandles`	List of power states that will disable this device power.
`status`	`string`	indicates the operational status of a device Legal values: `'ok'`, `'okay'`, `'disabled'`, `'reserved'`, `'fail'`, `'fail-sss'` See Important properties for more information.
`compatible`	`string-array`	compatible strings This property is required. See Important properties for more information.
`reg`	`array`	register space See Important properties for more information.
`reg-names`	`string-array`	name of each register space
`interrupts`	`array`	interrupts for device See Important properties for more information.
`interrupts-extended`	`compound`	extended interrupt specifier for device
`interrupt-names`	`string-array`	name of each interrupt
`interrupt-parent`	`phandle`	phandle to interrupt controller node
`label`	`string`	Human readable string describing the device (used as device_get_binding() argument) See Important properties for more information. This property is deprecated.
`clocks`	`phandle-array`	Clock gate information
`clock-names`	`string-array`	name of each clock
`#address-cells`	`int`	number of address cells in reg property
`#size-cells`	`int`	number of size cells in reg property
`dmas`	`phandle-array`	DMA channels specifiers
`dma-names`	`string-array`	Provided names of DMA channel specifiers
`io-channels`	`phandle-array`	IO channels specifiers
`io-channel-names`	`string-array`	Provided names of IO channel specifiers
`mboxes`	`phandle-array`	mailbox / IPM channels specifiers
`mbox-names`	`string-array`	Provided names of mailbox / IPM channel specifiers
`zephyr,deferred-init`	`boolean`	Do not initialize device automatically on boot. Device should be manually initialized using device_init().

Grandchild node properties

Name	Type	Details
`bias-high-impedance`	`boolean`	high impedance mode ("third-state", "floating")
`bias-pull-up`	`boolean`	enable pull-up resistor
`bias-pull-down`	`boolean`	enable pull-down resistor
`drive-push-pull`	`boolean`	drive actively high and low
`drive-open-drain`	`boolean`	drive with open drain (hardware AND)
`input-enable`	`boolean`	enable input on pin (e.g. enable an input buffer, no effect on output)
`pinmux`	`array`	An array of pins sharing the same group properties. Each element of the array is an integer constructed from the pin number and the alternative function of the pin. This property is required.
`drive-strength`	`string`	The drive strength of a pin, relative to full-driver strength. The default value is 0.1, which is the reset value of resigers PADREGx.PADnSTRNG and ALTPADCFGx.PADn_DS1. Default value: `0.1` Legal values: `'0.1'`, `'0.5'`, `'0.75'`, `'1.0'`
`ambiq,pull-up-ohms`	`int`	The 1.5K-24K pullup values are valid for select I2C enabled pads. For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49. The default value is 1500 ohms, which is the reset value of register PADREGx.PADxRSEL. Default value: `1500` Legal values: `1500`, `6000`, `12000`, `24000`
`ambiq,iom-nce-module`	`int`	IOM nCE module select, selects the SPI channel (CE) number (0-3). The default value is 0, which is the reset value of register CFGx.GPIOnOUTCFG. If the pin is not a CE, this descriptor will be ignored.
`ambiq,iom-mspi`	`int`	Indicates the module which uses specific CE pin, 1 if CE is IOM, 0 if MSPI. User should check g_ui8NCEtable in am_hal_gpio.c for the mapping information and config the pins accordingly, we give a default value 0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in ambiq hal. If the pin is not a CE, this descriptor will be ignored.
`ambiq,iom-num`	`int`	Indicates the instance which uses specific CE pin. IOM number (0-5) or MSPI (0-2). User should check g_ui8NCEtable in am_hal_gpio.c for the mapping information and config the pins accordingly, we give a default value 0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in ambiq hal. If the pin is not a CE, this descriptor will be ignored.